Abstract: A method for DC/DC conversion which comprises the steps of controlling a first switch (10) for coupling a supply terminal (5) to a first terminal (60) of an inductor (2) and a second switch (20) for coupling the first terminal (60) to a ground potential terminal (8). The method further comprises controlling a third switch (30) for coupling a second terminal (61) of the inductor (2) to the ground potential terminal (8) and a fourth switch (40) for coupling the second terminal (61) to an output terminal (6). A control sequence is used to control the four switches (10, 20, 30, 40) using four switching phases (A, B, C, D). A maximum of two switches out of the four switches (10, 20, 30, 40) change their switching position at a respective transition of subsequent switching phases (A, B, C, D).

Abstract: A circuit arrangement comprises a memory cell array (2) with at least one memory circuit (99). The memory circuit (99) comprises one non-volatile memory cell (98) inserted in a first current path (106) between a supply voltage terminal (9) and a reference potential terminal (8), and a volatile memory cell (97) inserted in a second current path (107) between the supply voltage terminal (9) and the reference potential terminal (8). The volatile memory cell (97) is coupled to the non-volatile memory cell (98) for reading the non-volatile memory cell (98).

Abstract: A multi-current-source comprises a voltage converter (VC), a first current source (CS1) with a first terminal (A1) which is adapted to be coupled to an output (OUT) of a voltage converter (VC) and with a second terminal (B1) which is adapted to be coupled to an input (IN) of the voltage converter (VC), at least a second current source (CS2) with a first terminal (A2) which is adapted to be coupled to the output (OUT) of the voltage converter (VC) and with a second terminal (B2) which is adapted to be coupled to the input (IN) of the voltage converter (VC), wherein the first current source (CS1) being adapted to provide a first load current (Il1) at its first terminal (A1) the first load current (Il1) being regulated to a first constant value and to provide a first unidirectional error current (Ierr1) at its second terminal (B1), wherein the at least one second current source (CS2) being adapted to provide a second load current (I12) at its first terminal (A2), the second load current (I12) being regulated to

Abstract: An amplification arrangement comprises a signal-processing element (SVE) with an integrator element (INT) that is coupled on the input side with a first input (E1) for feeding the input signal and with a second input (E2) for feeding a feedback signal. The signal-processing element (SVE) is designed to set a respective level of the input signal and/or the feedback signal as a function of a control signal. The amplifier arrangement furthermore comprises a pulse modulator (PM) that is designed to generate a pulse signal on a pulse output (POT) as a function of a signal applied on the output (SOT) of the signal-processing element (SVE). An output stage (OST) comprises a switching element (SW) that is designed to connect supply-voltage terminals (V1, V2, GND) to an output terminal (OOT) that is coupled with an amplifier output (AOT) and the second input (E2), and a control unit (CU) for driving the switching element (SW) that is coupled with the pulse output (POT).

Abstract: An electronic component (10a, 10b), with assignment of an address to the component, comprises a first terminal (A10a) for the application of a first signal (SCL) and a second signal (SDA) different from the first signal, and a second terminal (A10b), different from the first terminal, for the application of the first signal (SCL) and the second signal (SDA). Depending on the external connection of the first and second terminals (A10a, A10b), the component is assigned an address by means of which the component is addressable.

Abstract: A semiconductor body comprising a first connection for feeding an upper supply potential and a first and a second terminal cell, which are situated at a distance from each other. The semiconductor body further comprises an arrester structure, which is arranged between the first and second terminal cells in a p-doped substrate. The arrester structure comprises a first and a second p-channel field-effect transistor structure, each of which is set in a respective n-doped well substantially parallel to the first and second terminal cells, and a diode structure with a p-doped region set in a further n-doped well between the n-doped wells of the first and second p-channel field-effect transistor structures. The diode structure is designed to activate the first and second p-channel field-effect transistor structure as arrester elements during an electrostatic discharge in the semiconductor body.

Abstract: An oscillator arrangement is specified, in which a relaxation oscillator is refined to the extent that the comparator (2) to be used for comparing the voltage across a charge storage device (1) with a switching threshold (VTH) is a current comparator with two current branches (5, 6). One of these two current branches is used in the present case for guiding a charging or discharging current of the charge storage device (1). In this way, a current branch is eliminated, so that the proposed principle is preferably suitable for so-called ultra low power applications.

Abstract: An input circuit arrangement comprises an input, a comparator, and an evaluation circuit. The input is designed for coupling to a first terminal of an impedance and for feeding an input signal. The comparator is connected to the input of the input circuit arrangement and is designed for delivering an activation signal to an output as a function of a comparison of the input signal with an adjustable threshold. Furthermore, the evaluation circuit is connected to the input of the input circuit arrangement and for its activation to the output of the comparator and is designed for evaluating the value of the impedance that can be connected.

Abstract: The invention relates to a circuit arrangement (20) for a piezo transformer (22) comprising a driver circuit (23), to which the piezo transformer (22) can be connected, and a current sensor (21) for the determining an incoming power signal (IM), which is subject to an incoming current (IE) flowing through the piezo transformer (22). The invention further relates to the circuit arrangement (20) of a control unit (24) for providing a control signal (ST), which is subject the incoming power signal (IM); and an oscillator (25) having an oscillator output (43) for emitting an oscillator signal (SO) to a driver signal input (44) of the driver circuit (23) subject to the control signal (ST).

Abstract: A voltage converter (10) comprises an input (11) for receiving an input voltage (VIN), a first output (12) for providing a first output voltage (VPOS) and a second output (13) for providing a second output voltage (VNEG). The first output voltage (VPOS) and the second output voltage (VNEG) have opposite polarities. A switching arrangement (14) of the voltage converter (10) is designed to provide energy to an inductor (15) in a charging phase (A) of operation and to provide energy from the inductor (15) to the first output (12) and, via a flying capacitor (16), to the second output (13) in a discharging phase of operation. The first duration (t1) of the charging phase (A) of operation is controlled such that the difference between a first predetermined value and the sum of the absolute value of the first output voltage (VPOS) and of the second output voltage (VNEG) is minimized.

Abstract: A high voltage JFET has a deep well of a first type of conductivity made in a semiconductor substrate, a further well of an opposite second type of conductivity arranged in the deep well, a shallow well of a first type of conductivity arranged in the further well, a first contact region for source and a second contact region for drain arranged in the further well, a third contact region for gate arranged between the first contact region and the second contact region in the shallow well, a first distance between the first contact region and the third contact region being smaller than a second distance between the second contact region and the third contact region, and an electrical connection between the first contact region and the second contact region via at least one channel region present between the deep well and the shallow well in the further well.

Abstract: A light-sensitive component which has a semiconductor junction between a thin relatively highly doped epitaxial layer and a relatively lightly doped semiconductor substrate. Outside a light incidence window, an insulating layer is arranged between epitaxial layer and semiconductor substrate. In this case, the thickness of the epitaxial layer is less than 50 nm, with the result that a large proportion of the light quanta incident in the light incidence window can be absorbed in the lightly doped semiconductor substrate.

Abstract: A voltage regulator, comprising: an input terminal; an output terminal at which an output voltage is provided; an output transistor which couples the input terminal of the voltage regulator to the output terminal of the voltage regulator; and a transimpedance amplifier including an input terminal which is coupled to the output terminal of the voltage regulator and an output terminal which is coupled to a control terminal of the output transistor, optionally via a coupling, the coupling having an impedance value between the output terminal of the transimpedance amplifier and the control terminal of the output transistor which at a given frequency is smaller than or equal to an impedance value of an output impedance of the transimpedance amplifier.

Abstract: An arrangement for detecting a movement of a body, in which the body (20?) is mounted in such a way that it can move in at least one direction and in which a magnet (200) is incorporated. Its poles are aligned substantially parallel to a primary plane. A detector system is furthermore provided that comprises at least four magnetic field sensors (10a to 10d) for the detection of a change in the magnetic field when the body (20?) moves. In addition, a further magnetic field sensor (11) is provided for generating a correction signal that depends on the magnetic field. An evaluation unit (20) is used to provide movement information relating to the body (20?) derived from signals from the four magnetic field sensors (10a to 10d) and the minimum of one further magnetic field sensor (11).

Abstract: An amplifier with a non-linear current mirror comprises an amplification stage having an input terminal for an input signal as well as an output stage coupled to the amplification stage by a current mirror stage. The current mirror stage comprises at least one mirror transistor coupled to the amplification stage and at least one output transistor coupled to the output stage. The amplifier comprises two variable resistive elements, each of them connected in series to one of the mirror transistor and the output transistor. A tuning stage is adapted to tune the variable resistive elements in response to the input signal.

Abstract: A high voltage NMOS transistor is disclosed where the p-doped body is isolated against the p-doped substrate by a DN well having a pinch-off region where the depth of the DN-well is at minimum. By the forming space charge region at raising drain potentials a shielding of the drain potential results because the space charge region touches the field oxide between source and drain at the pinch-off region. An operation at the high side at enhanced voltage levels is possible.

Abstract: A circuit array controls operation of two loads that operate with a rectified AC voltage. The circuit array includes a semiconductor switch on a circuit path with the two loads and a control unit to generate a switch control signal that controls the semiconductor switch. The control unit includes a phase detection device to detect whether a phase of the AC voltage is positive or negative, and to output a detection signal that is based on whether the phase is positive or negative, and a logic unit to generate the switch control signal based on load control signals and the detection signal.

Abstract: A microphone amplifier comprises an input terminal (E100) for applying an input signal (IN), an output terminal (A100a) for outputting an output signal (OUT), and an additional output terminal (A100b) for outputting an additional output signal (VBIAS). The microphone amplifier also contains an amplifying circuit (10) for generating the output signal (OUT) by amplifying the input signal (IN), wherein the amplifying circuit (10) is connected between the input terminal (E100) and the output terminal (A100a), and a voltage generator (30) for generating the additional output signal (VBIAS). A supply voltage terminal (V30) of the voltage generator (30) is connected to the output terminal (A100a) of the microphone amplifier. Since the amplifying circuit (10) makes available a supply voltage (V) for the voltage generator (30), the microphone amplifier can be operated without a separate supply voltage terminal.

Abstract: A frequency divider and a method for frequency division are disclosed that can achieve a balanced duty cycle when performing a frequency division with an odd division ratio, independently of an input frequency.

Abstract: A circuit arrangement for temperature measurement comprises an input for connecting a temperature-sensitive element, a that is connected to a first input of a comparator. A reference voltage is connected to a second input of the comparator. Furthermore, the arrangement comprises a sequential logic, that is coupled to the output of the comparator that comprises a first output and a second output. A digitally controllable switch element for providing a superposition signal is connected to the output of the sequential logic and the first input of the comparator.