Abstract: A circuit arrangement for driving an electrical load comprises a connection node (LED) for connecting the electrical load and a control device (Ctrl) that is coupled to the connection node (LED) to drive the electrical load. A detection circuit (Det) is coupled to the connection node (LED) for detecting a trigger signal (trig) at the connection node (LED) and coupled to the control device (Ctrl) via a measurement channel (Mes).

Abstract: A transistor and a method for the fabrication of transistors with different gate oxide thicknesses is proposed, in which for the doping of the source, the typical LDD implantation, which is formed after the fabrication of the gate electrode, is replaced by a doping step, which is generated before applying the gate stack. In this way that is already a component of the remaining process sequence in the fabrication of the transistor doping can be used.

Abstract: A sensor arrangement has a plurality of Hall sensor devices, each configured to provide a sensor voltage in response to a magnetic field intensity. A selection unit is configured to forward either of the sensor voltages in response to a selection signal. A transconductance amplifier is configured to generate a sensing current depending on a forwarded sensor voltage. A filter stage has a resistor and a filter capacitor connected in parallel in a switchable manner in response to a first switching signal. The filter stage is configured to generate a filtered voltage across the filter capacitor depending on a sensing current. A capacitive analog-to-digital converter has an input capacitor being connected to the filter capacitor in a switchable manner in response to a second switching signal. The analog-to-digital converter is configured to generate a digital sensor value based on a filtered voltage.

Abstract: A voltage generator arrangement which comprises a voltage converter (40) and a polarity detection circuit (10). The voltage converter (40) is coupled to a supply voltage terminal (9) and an output terminal (7) and comprises a first mode of operation (P1) for a positive supply voltage (VIN) and a second mode of operation (P2) for a negative supply voltage (VIN). The polarity detection circuit (10) is coupled to the supply voltage terminal (9) and a control input terminal (47) of the voltage converter (40), for providing a first pilot signal (SP1) depending on the polarity of the supply voltage (VIN).

Abstract: A semiconductor arrangement has a semiconductor body (CP), comprising a semiconductor layer (HL) with a first (AB11, AB12) and at least one second (AB21, AB22) conducting terminal areas, respectively made in two parts, and with a first (TAB1) and a second (TAB2) test terminals; a first (KI1, KU1) and at least one second (KI2, KU2) contact areas, located on the semiconductor body (CP) and made of two parts, which are connected with the respective terminal areas (AB11, AB12; AB21, AB22), and a first (TK1) and a second (TK2) test contact areas that are connected with the respective test terminal areas (TAB1, TAB2); a first terminal (10) that can be arranged on the semiconductor body (CP) and that contacts both parts of the two-part first contact areas (KI1, KU1), and at least one second terminal (20) that can be placed on the semiconductor body (CP) and that contacts both parts of the at least one second two-part contact area (KI2, KU2), and a first (30) and a second (40) test terminals, which can be arranged on

Abstract: An arrangement and a method for temperature compensation for a resistance (1). A resistance (1) with a controllable resistance value is compared with a reference resistance (2) which is in the form of a switched capacitor. A comparator (3) compares the two resistance values with one another. The comparator (3) takes an error signal as a basis for actuating the controllable resistance (1). This produces a thermally stable resistance. The principle can preferably be applied in transimpedance amplifiers.

Abstract: A circuit arrangement for protection against electrostatic discharges has a diverting structure (ESD1), which comprises a diverting element (DE1) and a switchable element (SW1). The diverting element (DE1) is set up to drain off an electrostatic discharge between a first and a second terminal (K1, K2). The switchable element (SW1) can take a first and a second switching state, where a function of the diverting element (DE1) can be activated depending on the switching state of the switchable element (SW1).

Abstract: A circuit arrangement for shifting a voltage level comprises a data-current converter (2) that is connected to a first connection (K1) and that has an input for feeding a digital input data signal (DIN), a first output for providing a current (I), and also a second output for providing a reference current (I1), and a current-data converter (3) that is connected to a second connection (K2) and that has a first input for feeding the current (I), a second input for feeding the reference current (I1), and also an output for providing a digital output data signal (DOUT). Here, a voltage level of the digital output data signal (DOUT) is different from a voltage level of the digital input data signal (DIN). In addition, a method for shifting a voltage level is provided.

Abstract: The oscillator arrangement (1) comprises a differential amplifier (13) and also a first and a second terminal (2, 3). The first terminal (2) of the oscillator arrangement (1) can be coupled via a quartz resonator (10) to the second terminal (3) of the oscillator arrangement (1) and via a first capacitor (11) to a reference voltage terminal (8). The second terminal (3) of the oscillator arrangement (1) can be coupled via a second capacitor (12) to the reference voltage terminal (8). The differential amplifier (13) is connected at a first input (14) to the first terminal (2) of the oscillator arrangement (1) and at an output (16) to the second terminal (3) of the oscillator arrangement (1). The second input (15) of the differential amplifier (13) is connected via a direct voltage source (21) to the reference voltage terminal (8).

Abstract: An amplifier arrangement comprises a signal input (Iin+, Iin?) to receive a signal to be amplified, a signal output (Out) to provide an amplified signal, an amplifier stage (AS) coupled between the signal input (Iin+, Iin?) and the signal output (Out), a switchable dynamic biasing stage (DB) with an input coupled to the signal input (Iin+, Iin?), a switchable gain boosting stage (GB) with an input coupled to the signal input (Iin+, Iin?), and a switching device (SD) coupled to the amplifier stage (AS) such that either an output of the switchable dynamic biasing stage (DB) or an output of the switchable gain boosting stage (GB) are coupled to the amplifier stage (AS). In one embodiment, by enabling the switchable dynamic biasing stage (DB) in an initial large-signal phase of amplification and the switchable gain boosting stage (GB) in a latter small-signal phase of amplification by means of the switching device (SD), high gain and low current consumption are simultaneously realised.

Abstract: In a measurement method, a plurality of magnetic field sensors (MS0-MS15) that are arranged along a circular periphery (CIR) and are each configured to emit a sensor signal (H0-H15) as a function of a magnetic field intensity is provided. A diametrically magnetized magnetic source (MAG) seated rotatably on the circular periphery (CIR) about an axis of rotation (RA) is further provided. A first set of sensor signals from the magnetic field sensors (MS0-MS15) is received and a first orientation (AL1) of an axis (AX) defined by a reference value transition (RFD) is determined as a function the first set. After a rotation of the magnetic source (MAG) about the axis of rotation (RA), a second set of sensor signals is received and a second orientation (AL2) of the axis (AX) is determined as a function of the second set of sensor signals. A position (X0, Y0) of the axis of rotation (RA) is acquired as a function of the first and the second orientation (AL1, AL2).

Abstract: In one embodiment, a circuit arrangement with a column latch has a first terminal (A1) for connection to a bit line (BL) of a nonvolatile memory, a second terminal (A2) connected via a first switchable path (P1) to a reference-potential terminal (VSS) and via a second switchable path (P2) to a supply-potential terminal (VPP), and the column latch (100, 110), which is coupled to the second terminal (A2) and is adopted for storing a potential at the second terminal (A2). The first terminal (A1) is coupled to the second terminal (A2) via a first switchable connection (L1) and via a second switchable connection (L2). A method for operating a column latch is additionally disclosed.

Abstract: An analogue/digital converter arrangement and a method. A differential input voltage is converted by means of a differentially implemented capacitative voltage divider that comprises two programmable capacitor banks (3, 4), and with the aid of the comparator (6) into a digital output signal.

Abstract: A well (2) doped for a conductivity type and provided as the sensor region is formed in a substrate (1) made of semiconductor material. Contact regions (4), arranged spaced apart from one another and doped for the same conductivity type as the well (2), are formed in a cover layer (3) that delimits the region with the conductivity type of the well. The contact areas (4) are electroconductively connected to the well (2) and provided for terminal contacts (6).

Abstract: A method includes a voltage converter outputting an output voltage that is based on an input voltage and on a first multiplication factor, determining a predicted current sink voltage based on a new multiplication factor obtained from a set of selectable values, based on a signal derived from the input voltage, based on a load voltage across an electrical load, and based on a correction voltage. The method also includes comparing a predicted current sink voltage with a predetermined threshold value and outputting the new multiplication factor to a control input of the voltage converter if the predicted current sink voltage exceeds the predetermined threshold value.

Abstract: An n-conductively doped source region (2) in a deep p-conducting well (DP), a channel region (13), a drift region (14) formed by a counterdoping region (12), preferably below a gate field plate (6) insulated by a gate field oxide (8), and an n-conductively doped drain region (3) arranged in a deep n-conducting well (DN) are arranged in this order at a top side of a substrate (1). A lateral junction (11) between the deep p-conducting well (DP) and the deep n-conducting well (DN) is present in the drift path (14) in the vicinity of the drain region (3) so as to avoid a high voltage drop in the channel region (13) during the operation of the transistor and to achieve a high threshold voltage and also a high breakdown voltage between source and drain.

Abstract: A component comprising a semiconductor junction (HU) is proposed which is formed from crystalline doped semiconductor layers. A semiconductor circuit (IC) is formed on the surface of the component, and a diode is formed internally and directly below the circuit. Integrated circuit and diode are connected to one another and formed and integrated diode component, in particular a photodiode array.

Abstract: A frequency divider comprises a cascade of at least two triggered delay elements (FF1, FF2, . . . ), a reference frequency input (FIN) and a clock output (FOUT). The triggered delay elements (FF1, FF2) are configured to forward a state of an input signal at a respective data input (D1, D2) to a respective data output (Q1, Q2) either for a rising clock edge of a clock signal at a respective clock input (C1, C2) or for a falling clock edge of the clock signal, depending on a control signal at a respective trigger control input (PH1, PH2). Clock inputs (C1, C2) of the delay elements (FF1, FF2) are coupled to the reference frequency input (FIN). The data input (D1) and the trigger control input (PH1) of the first delay element (FF1) of the cascade are coupled to the data output (Q2, QN) of the last delay element (FF2, FFN) of the cascade. The data input (D2, . . . ) and the trigger control input (PH2, . . . ) of further delay elements (FF2, . . . ) of the cascade are coupled to the data output (Q1, . . .

Abstract: A method for manufacturing a semiconductor body with a trench comprises the steps of etching the trench (11) in the semiconductor body (10) and forming a silicon oxide layer (12) on at least one side wall (14) of the trench (11) and on the bottom (15) of the trench (11) by means of thermal oxidation. Furthermore, the silicon oxide layer (12) on the bottom (15) of the trench (11) is removed and the trench (11) is filled with polysilicon that forms a polysilicon body (13).

Abstract: A circuit arrangement (10) for driving an electrical load (2) comprises an input (11) for feeding a power-supply voltage (Vs) with an AC component and an output (13) for providing an output signal (Sout) for driving a connectable electrical load (2). The circuit arrangement (10) further comprises a frequency processing circuit (20) for proving a reference frequency (f1) as a function of the AC component, and a demodulator (60) with a first input (61) for feeding the reference frequency (f1), with a second input (62) that is coupled to the input (11) of the circuit arrangement (10), and with an output (63) that is coupled to the output (13) of the circuit arrangement (10).