Abstract: An oscillator circuit comprises a charging block with a first terminal for feeding a first charging current, to which terminal a first capacitor and a series circuit of a first and a second switch are connected, and with a second terminal for feeding a second charging current, to which terminal a second capacitor and a series circuit of a third and a fourth switch are connected, as well as a comparison circuit with a first and a second comparator. The comparators are configured to compare voltages at the first and second terminals to a reference voltage, wherein their output is connected to control terminals of the third or first switch. The oscillator circuit further comprises a flipflop that is coupled on the input side to the outputs of the first and second comparators, and on the output side, to control terminals of the second and fourth switches, as well as to an oscillator output.

Abstract: A microphone arrangement comprises a stack arrangement (1) which comprises a first semiconductor body (10) having a microphone structure (13) and a second semiconductor body (80). The second semiconductor body (80) comprises a first main face (81) on which an integrated circuit (83) is arranged and a second main face (82) which faces the first semiconductor body (10).

Abstract: In one embodiment, a readout circuit for rewritable memories comprises a control logic unit with an input for supplying a start signal and with several outputs for providing a respective control signal as a function of start signal, a first terminal for switchable connection to a first memory cell by means of a first switch, and a second terminal for switchable connection by means of a second switch to a second memory cell, and a readout unit coupled to the control logic unit, as well as to the first and second terminals, with an output for providing an output signal as a function of a state of the first and/or the second memory cell and as a function of the control signals, wherein the readout circuit is designed for self-terminating operation in a reading mode and in a test mode. A readout method for rewritable memories is additionally provided.

Abstract: A voltage regulator (10) comprises a first transistor (13) which couples an input terminal (11) of the voltage regulator (10) to an output terminal (12) of the voltage regulator (10) and a second transistor (16). The first and the second transistors (13, 16) form a current mirror structure. Further on, the voltage regulator (10) comprises a control node (17) which is coupled to the input terminal (11) of the voltage regulator (10) via the second transistor (16) and which is coupled to the output terminal (12) of the voltage regulator (10) via a feedback circuit (28). Furthermore, the voltage regulator (10) comprises an amplifier (22) with an input terminal (23) which is coupled to the control node (17) and an output terminal (24) which is coupled to a control terminal (21) of the second transistor (16).

Abstract: A controller includes a control circuit. The control circuit includes a forward path that includes an input and an output, a feedback path coupled to the output and to the input, and a sensor that is between the input and the output. The sensor generates a sensor signal based on an input signal applied to the input. The forward path generates an output signal based on the sensor signal. The output signal is sent along the feedback path to the input of the forward path. The controller also includes a detector that obtains an intermediate signal from the forward path between the input and the output. The detector generates a control signal using the intermediate signal. The forward path includes a control device that limits the output signal to a predetermined value. The detector controls the control device using the control signal.

Abstract: A circuit arrangement for operating voltage detection has a detection block (1) and a control block (2). Detection block (1) has a first transistor (P1) that is connected between a first supply voltage terminal (VDD) and a first node (K1) and has a first control terminal (S1), a first resistor element (R1) that is connected between first node (K1) and second supply voltage terminal (VSS), a second transistor (P2) that is connected between first supply voltage terminal (VDD) and a second node (K2) and has a second control terminal (S2), a second resistor element (R2) that is connected between second node (K2) and second supply voltage terminal (VSS), a first switch (N1) that connects first node (K1) to second control terminal (S2), and a third resistor element (R3) that is connected between second control terminal (S2) and first supply voltage terminal (VDD).

Abstract: A power supply arrangement (10) comprises a voltage regulator (11), a driver circuit (28), and a control circuit (32). The voltage regulator (11) has a voltage regulator input (12) for the feeding of an input voltage (VIN), a voltage regulator output (13) to which an electrical load (20) is coupled that comprises a current source (21), a feedback input (14), and a comparator (15) that is coupled at a first input to the feedback input (14). The driver circuit (28) has a driver output (30) that is connected to a control terminal of the current source (21). The control circuit (32) comprises a control comparator (33) that is coupled at a first input with a signal output (44) of the driver circuit (28) and at an output with the feedback input (14) and also to which, at a second input, a reference signal (SR) can be fed.

Abstract: In one embodiment, a charging circuit for a charge accumulator comprises a first terminal (A1) for supplying a charging voltage (UC) and for connecting the charge accumulator (SC) connected to a reference potential terminal (10), a second terminal (A2) for providing a load voltage (UD) and for connecting an electrical load (D1), a control assembly (ST) which is coupled to the first and the second terminals (A1, A2) and has a signal output (A3) for providing a first charge state signal (S1) and a test output (TA) for providing at test signal (on), and a current source (I1) that is coupled to the second terminal (A2), wherein the first charge state signal (S1) is provided depending on a value of an additional voltage (U12) between the first and the second terminals (A1, A2) and depending on the test signal (on), and wherein the charging voltage (UC) is supplied depending on the first charge state signal (S1). The invention also relates to a method for charging a charge accumulator.

Abstract: An arrangement for charge integration comprises an input (1) for the provision of a charge-dependent signal and an integrator (30) to integrate a signal present at its input. In addition, a coupling circuit (20) that can adopt at least two operating states is provided to couple the input (1) to the integrator (30) which has a temperature-dependent coupling characteristic. A correction circuit (10) that can be operated by a clock signal is coupled to the input (1) in order to transfer a quantity of charge, and has a temperature characteristic that is derived from the coupling characteristic of the coupling circuit (20).

Abstract: A method for DC/DC conversion comprises operating in a Boost mode of operation or in a Buck-Boost mode of operation. Furthermore, the method comprises switching from the Boost mode of operation to the Buck-Boost mode of operation, if a desired value (VOUTR) of an output voltage (VOUT) which is generated from a supply voltage (VIN) by the DC/DC conversion is smaller than a first reference voltage (VR1). The method also comprises switching from the Buck-Boost mode of operation to the Boost mode of operation, if the desired value (VOUTR) is larger than a second reference voltage (VR2).

Abstract: A chip design (1) comprising an external supply connection (VBAT), an internal supply connection (VDD), an integrated circuit (2) that is coupled to the internal supply connection (VDD) for voltage supply, and a fuse (3) that electrically connects the internal supply connection (VBAT) and is arranged within the chip design (1).

Abstract: A power source arrangement comprises a controlled and clocked operated power source, that power source providing an output voltage out of a plurality of output voltages in response to a first multiplication factor. One or more regulated current sources are connected to the controlled and clocked operated power source to provide an output current to respective loads. Each of the one or more regulated current sources is adapted to provide a first indication signal upon a regulated operation of the respective current source. The power source arrangement further comprises a dummy power source as well as a dummy current source connected to the dummy power source. The dummy current source receives a load signal corresponding to a voltage drop over the loads connected to the one or more regulated current sources and provides a second indication signal in response thereto.

Abstract: A method for offset compensation of a switched-capacitor amplifier comprises a reset phase (?1) and at least one working phase (?2). An output voltage (Vout) of the amplifier (amp) is fed according to a damped feedback loop gain (AB(1)) to a first amplifier input (ain1) in the reset phase (?1) as a function of an offset voltage (Voff). In the least one working phase (?2), an offset of the amplifier (amp) is compensated as a function of the offset voltage (Voff) by superimposing the output voltage (Vout) onto an input voltage (Vin) of the amplifier (amp) according to a loop gain (AB(2)).

Abstract: A circuit for converting an alternating voltage into a rectified voltage includes a first transistor having a first terminal, a second terminal, and a control terminal. The first terminal is configured to receive the alternating voltage via an input terminal, and the second terminal is electrically coupled to an output terminal for outputting the rectified voltage. A control circuit includes a first input, a second input, and a first output. The first input is electrically coupled to the first terminal of the first transistor, the second input is electrically coupled to the second terminal of the first transistor, and the first output is coupled to the control terminal of the first transistor. The control circuit is configured to generate a first control signal based on a first voltage at the first input and based on a second voltage at the second input. The conversion circuit also includes a resistive circuit.

Abstract: A photodiode in which a pn junction is formed between the doped region (DG) formed in the surface of a crystalline semiconductor substrate and a semiconductor layer (HS) deposited above said doped region. An additional doping (GD) is provided in the edge region of the doped zone, by means of which additional doping the pn junction is shifted deeper into the substrate (SU). With the greater distance of the pn junction from defects at phase boundaries that is achieved in this way, the dark current within the photodiode is reduced.

Abstract: A high-voltage transistor is provided with a well of a first conductivity type, which is arranged in a substrate (10) of a second conductivity type, with a source (14), a drain (12), and a gate electrode (18) above a channel region (KN, KP) formed between the source and the drain, wherein several staggered and nested wells (11, 13, 15, 17) of the same conductivity type extend from the source (14) or the drain (12) into the substrate (10) and wherein the doping concentration (log c) of the wells essentially decreases and is smoothed from the substrate surface with increasing depth (T) and also laterally. In this way, field-strength increases and also unintentional breakdown are prevented. Furthermore, a production method is specified.

Abstract: A voltage converter comprises a first, a second and a third capacitor (11, 12, 13) which are switched in series in at least one operating state, an input (1) for supplying an input voltage (VIN), an output (2) for providing an output voltage (VOUT), and a compensation circuit (5). The input (1) of the voltage converter is coupled to a capacitor from a group comprising the first, the second and the third capacitor (11, 12, 13). The output (2) of the voltage converter is coupled to a capacitor from the group comprising the first, the second and the third capacitor (11, 12, 13). The compensation circuit (5) is coupled to the first, the second and the third capacitor (11, 12, 13) and adapts a first voltage (V1) of the first capacitor (11), a second voltage (V2) of the second capacitor (12) and a third voltage (V3) of the third capacitor (13) to one another.

Abstract: A semiconductor circuit in a semiconductor body and a wafer bonding method for connecting the semiconductor circuit to another substrate, in which a diode is realized in a laminar structure. The semiconductor circuit is connected to the terminals of the diode by means of feedthroughs that extend through the semiconductor body.

Abstract: A control circuit for control of light-emitting diodes has a first LED string (50) with at least one LED (51, 52, 53) and a first supply device (1) for supply of current to the first LED string (50). The supply device (1) has a control input (10) for delivery of a first control signal (CTL) and is provided for delivery, as desired, of a first supply current (IV1) or a second supply current (IV2) in dependence on the first control signal (CTL). The first and the second control currents (IV1, IV2) are non-zero.

Abstract: A sensor arrangement has a sensor array (SA) with a first, a second, and a third sensor focus (SSP1, SSP2, SSP3), which are located along a main linear direction (L) and in which the third sensor focus (SSP3) is located in the middle between the first and second sensor foci (SSP1, SSP2). Individual sensor devices (SM1, SM2, SM3) with magnetic field sensors that provide a first, second, and third set of sensor signals are correlated with the sensor foci (SSP1, SSP2, SSP3). A first and a second channel signal (CH1, CH2) are derived as a function of the sets of sensor signals in a processing device (PRC) via a first and a second combination device (K1, K2). An evaluation unit (EV) is configured to derive a phase angle as a function of the channel signals (CH1, CH2).