Patents Assigned to Avago Technologies General IP Pte. Ltd.
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Publication number: 20140079410Abstract: In an optical data communication system transmitter, in which a laser is driven with a laser modulation signal in response to a serial data stream, the laser driver adds peaking to a bit other than the first bit following a bit transition.Type: ApplicationFiled: September 20, 2012Publication date: March 20, 2014Applicant: Avago Technologies General IP Pte. LtdInventors: Xiaozhong Wang, David Chak Wang Hui
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Patent number: 8035119Abstract: A discontinuity-containing, light-diffusing substrate is placed within an LED light source. In one embodiment, the substrate is placed between an LED light source and a light guide. The light diffusing substrate may include a plurality of air bubbles, grooves or both, effective to mix the colored light and yield a white light exiting the light guide. Methods of constructing optical devices and light sources having a bubble-containing substrate are also disclosed.Type: GrantFiled: October 3, 2006Date of Patent: October 11, 2011Assignee: Avago Technologies General IP Pte, Ltd.Inventors: Fook Chin Ng, Siew It Pang, Ju Chin Poh, Sundar A. L. N. Yoganandan, Tong Fatt Chew, Thye Linn Mok
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Patent number: 7423487Abstract: A variable gain feedback amplifier circuit comprising a degenerated common emitter circuit coupled to an emitter follower circuit, an output of the emitter follower circuit being coupled to an input of the degenerated common emitter circuit via a variable feedback impedance. An automatic gain controller is coupled to the variable feedback impedance in order to reduce a closed loop gain of the variable gain feedback amplifier circuit when required. The degenerated common emitter circuit also comprises a variable emitter impedance that is also controlled by the automatic gain controller so as to counteract a lowering effect of a reduction in the variable feedback impedance on the open-loop gain of the variable gain feedback amplifier circuit.Type: GrantFiled: June 29, 2006Date of Patent: September 9, 2008Assignee: Avago Technologies General IP Pte LtdInventors: Marco Fornasari, Fesseha Tessera Seifu, Samir Aboulhouda
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Patent number: 7424120Abstract: A method and apparatus for generating and controlling volume of a speaker of an appliance is disclosed. The appliance includes an IC chip connected to an amplifier subsystem. The IC chip includes a square-wave audio signal generator, a counter, a register, a comparator, and an AND gate. Theses components of the IC chip are used to generate modulated audio frequency square-wave signal. The modulated audio frequency square-wave signal having pulses, each pulse has a width determined by the volume control value. The modulated audio frequency square-wave signal is sent from the IC chip to the amplifier subsystem on a single connection. At the amplifier subsystem, the modulated audio frequency square-wave signal is integrated over, filtered, and amplified to drive a speaker to produce the desired sound. By adjusting the volume control value, the widths of the pulses, thus the volume of the produced sound can be controlled.Type: GrantFiled: August 6, 2003Date of Patent: September 9, 2008Assignee: Avago Technologies General IP Pte LtdInventor: Douglas Gene Keithley
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Patent number: 7418025Abstract: A wavelength of an optical source is monitored by first and second adjacent detectors on a common base. A bulk reflective component has first and second partially reflective surfaces that respectively direct first and second portions of energy from the source to the first and second detectors. A wavelength discriminator is positioned between the first detector and first surface. An optical isolator downstream of the reflective component prevents radiation from the source and exiting the component from being coupled to the detectors and back to the source.Type: GrantFiled: March 17, 2003Date of Patent: August 26, 2008Assignee: Avago Technologies General IP Pte LtdInventor: Andrew Harker
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Patent number: 7412122Abstract: An integrated circuit cast on a single die having a plurality of receivers in a receiver region, a plurality of transmitters in a transmitter region, and a spatial separation region having a plurality of n-type and p-type subregions disposed on the single die to separate the transmitter region from the receiver region. The pn-junctions between the n-type and p-type subregions are reverse-biased thereby reducing or eliminating coupling of noise and crosstalk between the transmitter and receiver is reduced.Type: GrantFiled: March 15, 2006Date of Patent: August 12, 2008Assignee: Avago Technologies General IP Pte LtdInventors: Matthew Scott Abrams, Young Gon Kim, Myunghee Lee, Stefano Therisod, Robert Elsheimer
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Patent number: 7405109Abstract: A method for manufacturing a layered structure for routing electrical signals comprising the steps of providing a layout for the layered structure having an insulating layer with at least one signal trace, a via, and a stub trace on a first side of the insulating layer, and a generally planar electrically conductive layer disposed on a second side of the insulating layer. Identify the stub trace and define a beneficial portion on the second side based upon a layout of the stub trace where the electrically conductive layer on the second side is to be absent. Modify the layout according to the step of defining and manufacture the layered structure according to the modified layout.Type: GrantFiled: December 14, 2004Date of Patent: July 29, 2008Assignee: Avago Technologies General IP Pte LtdInventor: William S Burton
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Patent number: 7401108Abstract: A random noise signal generator circuit comprising a random noise source that produces a random noise signal, an amplification circuit that amplifies the random noise signal to produce an amplified random noise signal, a feedback loop having a DC offset correction circuit, and a summer. The DC offset correction circuit processes a fed back portion of the amplified random noise signal to produce a DC offset correction signal. The summer sums the random noise signal produced by the random noise source and the DC offset correction signal to produce a summed signal. The summer is electrically coupled to the amplification circuit for providing the summed signal to the amplification circuitry. The amplification circuitry amplifies the summed signal to produce a random noise output signal.Type: GrantFiled: September 21, 2004Date of Patent: July 15, 2008Assignee: Avago Technologies General IP Pte LtdInventor: Robert H. Miller, Jr.
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Patent number: 7400036Abstract: A semiconductor chip package includes a package substrate having a first bond pad pattern. A semiconductor chip resides on the package substrate. The semiconductor chip has a second bond pad pattern. A lid cover houses the semiconductor chip and is fitted onto the package substrate. The second bond pattern of the semiconductor chip is connected to the first bond pattern of the package substrate through internal conductor traces of the lid cover.Type: GrantFiled: December 16, 2002Date of Patent: July 15, 2008Assignee: Avago Technologies General IP Pte LtdInventor: Say Leong Tan
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Patent number: 7399955Abstract: An apparatus having a coherent light source, an optical sensor, and a controller that can be utilized in optical mice and the like is disclosed. The coherent light source emits coherent light in a cone of angles about an illumination direction. The optical sensor includes an array of photodetectors disposed on a die having a surface substantially perpendicular to the illumination direction. The controller compares first and second images recorded by the optical sensor at different times and determines a displacement indicative of the direction and distance the apparatus has moved between the two different times. A portion of the coherent light source is bonded to the die at a location within the array of photodetectors.Type: GrantFiled: April 18, 2006Date of Patent: July 15, 2008Assignee: Avago Technologies General IP Pte LtdInventors: Hun Kwang Lee, Sai Mun Lee, A/L Gopal Krishnan Thineshwaran
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Patent number: 7401315Abstract: A method for implementing package-level intellectual property (PLIP) preverification for system on chip (SOC) devices includes providing at least one externally connected intellectual property (IP) core with an SOC. A package generic unit is provided with the IP core and is configured for providing external interface functions with respect to the SOC, wherein said package generic unit is pre-verified in silicon and independent of the specific packaging of the SOC. A package adaptation unit is provided with the IP core and is configured for providing external interface functions with respect to the SOC, wherein the package adaptation unit is pre-verified in silicon and dependent upon the specific packaging of the SOC.Type: GrantFiled: November 14, 2005Date of Patent: July 15, 2008Assignee: Avago Technologies General IP Pte LtdInventors: Haoran Duan, Charles Evans, Michael Alvin Rencher, James R. Emmert
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Patent number: 7400272Abstract: A hybrid binary/thermometer code is employed to adjust the output impedance of a variable impedance output driver circuit having an impedance network comprising a plurality of impedance legs each programmably electrically connectable according to the hybrid binary/thermometer code in parallel between a voltage source and the signal pad. The plurality of impedance legs are partitioned into one or more set pairs of binary stepped impedance legs and corresponding thermometer stepped impedance legs. A binary set of calibration signals in the hybrid binary/thermometer code steps a given set of binary stepped impedance legs according to a binary code and a thermometer set of calibration signals in the hybrid binary/thermometer code steps the corresponding set of thermometer stepped impedance legs according to a thermometer code once per full count iteration of the binary set of calibration signals.Type: GrantFiled: June 10, 2006Date of Patent: July 15, 2008Assignee: Avago Technologies General IP Pte LtdInventors: Guy Harlan Humphrey, David Lawrence Linam
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Patent number: 7391512Abstract: An optoelectronic system for measuring fluorescence or luminescence emission decay, including (a) a light source being a light emitting diode, a semiconductor laser or a flash tube; (b) a first integrated circuit comprising at least one circuit causing the light source to emit light pulses towards a sample which causes a fluorescence or luminescence emission from the sample; (c) a photodiode detecting the emission; (d) a second integrated circuit comprising a detection analysis system determining information about the sample by analyzing decay of the detected emission; and (e) an enclosure enclosing the light source, the first integrated circuit, the second integrated circuit and the photodiode.Type: GrantFiled: December 22, 2004Date of Patent: June 24, 2008Assignee: Avago Technologies General IP Pte. Ltd.Inventors: Julie E Fouquet, Ian Hardcastle, Rene P Helbing, Annette C. Grot, John Francis Petrilla
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Patent number: 7386824Abstract: Systems and methods are disclosed herein for determining the placement of a standard cell, representing a semiconductor component in a design stage, on an integrated circuit die. One embodiment of a method, among others, comprises analyzing regions of a semiconductor die with respect to the susceptibility of the region to be exposed to radiation. This method further comprises placing the standard cell in one of the analyzed regions of the semiconductor die, the standard cell being placed based on the sensitivity of the standard cell to radiation. The method may also comprise running an algorithm, e.g. using a component placement engine, for determining the placement of semiconductor components on an integrated circuit die.Type: GrantFiled: July 26, 2005Date of Patent: June 10, 2008Assignee: Avago Technologies General IP Pte LtdInventors: Howard L. Porter, Richard S. Rodgers, Troy H. Frerichs
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Patent number: 7386413Abstract: A testing apparatus includes one or more trace banks. Each trace bank includes (1) an input switch operable to couple an input port to one of multiple output ports, (2) an output switch operable to couple one of multiple input ports to one output port, and (3) transmission lines of different lengths coupled between the output ports of the input switch and the input ports of the output switch. The trace banks can be cascaded using cables to connect their output and input ports. The input and output switches in the trace banks are controlled to provide a transmission path of the desired length.Type: GrantFiled: April 28, 2005Date of Patent: June 10, 2008Assignee: Avago Technologies General IP Pte LtdInventor: Jeff P. Kirsten
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Patent number: 7382210Abstract: Disclosed are various devices, systems and methods for testing broadband differential coupling circuits that are capable of measuring the amount of extraneous interference and noise in such circuits. In preferred embodiments, NEXT and FEXT crosstalk performance characteristics of differential coupling circuits are provided.Type: GrantFiled: September 29, 2005Date of Patent: June 3, 2008Assignee: Avago Technologies General IP Pte. LtdInventors: T. Shannon Sawyer, Minh V. Quach
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Patent number: 7378643Abstract: An Optical Projecting Encoder (“OPE”) having an emitter module for transmitting emitted optical radiation through a mask to a moving object, and a detector module for receiving reflected optical radiation from the moving object. The reflected optical radiation from the moving object may include a predetermined image cast by the mask and a surface texture image from the moving object. The OPE may include a transmissive layer covering both the emitter module and the detector module, where the transmissive layer covering the emitter module collimates the optical radiation from the emitter module, and the transmissive layer covering the detector module concentrates the optical radiation reflected from the moving object to the detector module. The detector module may include an optical navigation sensor that continuously acquires and compares predetermined images cast by the mask and surface texture images from the moving object.Type: GrantFiled: April 24, 2006Date of Patent: May 27, 2008Assignee: Avago Technologies General IP Pte LtdInventors: Chee Foo Lum, Sai Mun Lee, Weng Fei Wong
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Patent number: 7374348Abstract: An optoelectronic device having a hermetically sealed optoelectronic component and to a method of forming the device, which may for example be an optical transmitter or receiver device for use in a fiber optic communications network. The optoelectronic device comprises a first sub-assembly and a second sub-assembly, the first sub-assembly comprising at least one optoelectronic component. The optoelectronic component is optically aligned with the at least one optical element along an optical axis to form a housing for the optoelectronic component, the sub-assemblies being joined by at least two joins across the interface including at least one non-hermetic join and separate from the non-hermetic join(s) a hermetic join that extends fully around the optical axis to seal hermitically the optoelectronic component within the housing.Type: GrantFiled: June 27, 2006Date of Patent: May 20, 2008Assignee: Avago Technologies General IP Pte LtdInventors: Mark Jeffrey Dunn, David John Kenneth Meadowcroft
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Patent number: 7367095Abstract: Embodiments of an acoustically-coupled transformer have a first stacked bulk acoustic resonator (SBAR) and a second SBAR. Each of the SBARs has a lower film bulk acoustic resonator (FBAR) and an upper FBAR, and an acoustic decoupler between the FBARs. The upper FBAR is stacked atop the lower FBAR. Each FBAR has opposed planar electrodes and a piezoelectric element between the electrodes. The piezoelectric element is characterized by a c-axis. The c-axes of the piezoelectric elements of the lower FBARs are opposite in direction, and the c-axes of the piezoelectric elements of the upper FBARs are opposite in direction. The transformer additionally has a first electrical circuit connecting the lower FBAR of the first SBAR to the lower FBAR of the second SBAR, and a second electrical circuit connecting the upper FBAR of the first SBAR to the upper FBARs of the second SBAR.Type: GrantFiled: April 14, 2006Date of Patent: May 6, 2008Assignee: Avago Technologies General IP Pte LtdInventors: John D. Larson, III, Yury Oshmyansky
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Patent number: 7365407Abstract: A packaged circuit and method for packaging an integrated circuit are disclosed. The packaged circuit has a lead frame, an integrated circuit chip, and an encapsulating layer. The lead frame has first and second sections, the first section including a lateral portion, a chip mounting area and a first extension. The integrated circuit chip is mounted in the chip mounting area and is in thermal contact with the chip mounting area. The encapsulating layer has top, bottom, and first and second side surfaces. The first extension is bent to provide a first heat path from the chip mounting area to the bottom surface. The heat path connects the heat chip mounting area to the bottom surface without passing through the first and second side surfaces and provides a heat path that has less thermal resistance than the heat path through either the lateral portion or the second section.Type: GrantFiled: May 1, 2006Date of Patent: April 29, 2008Assignee: Avago Technologies General IP Pte LtdInventors: Kee Yean Ng, Hui Peng Koay, Chiau Jin Lee, Kheng Leng Tan, Wei Liam Loo, Keat Chuan Ng, Alzar Abdul Karim Norfidathul