Patents Assigned to Avago Technologies General IP Pte. Ltd.
  • Patent number: 7279718
    Abstract: A photonic crystal light emitting diode (“PXLED”) is provided. The PXLED includes a periodic structure, such as a lattice of holes, formed in the semiconductor layers of an LED. The parameters of the periodic structure are such that the energy of the photons, emitted by the PXLED, lies close to a band edge of the band structure of the periodic structure. Metal electrode layers have a strong influence on the efficiency of the PXLEDs. Also, PXLEDs formed from GaN have a low surface recombination velocity and hence a high efficiency. The PXLEDs are formed with novel fabrication techniques, such as the epitaxial lateral overgrowth technique over a patterned masking layer, yielding semiconductor layers with low defect density. Inverting the PXLED to expose the pattern of the masking layer or using the Talbot effect to create an aligned second patterned masking layer allows the formation of PXLEDs with low defect density.
    Type: Grant
    Filed: January 28, 2002
    Date of Patent: October 9, 2007
    Assignees: Philips Lumileds Lighting Company, LLC, Avago Technologies General IP Pte. Ltd.
    Inventors: Michael R. Krames, Mihail M. Sigalas, Jonathan J. Wierer, Jr.
  • Patent number: 7281178
    Abstract: A system and method for write-enable bypass testing in an electronic circuit. According to one embodiment, the integrated circuit that includes a memory block having at least one input and at least one output. At least one input is associated with a block of input logic and at least one output is associated with a block of output logic. The integrated circuit also includes a test circuit coupled to the memory block and operable to verify the block of input logic and the block of output logic while at the same time not impacting the timing of the integrated circuit. As such a signal propagating through just the input logic, the memory block and the output logic does so in an amount of time substantially similar the time it takes to propagate through the input logic, the memory block, the output logic, and the test circuit.
    Type: Grant
    Filed: July 15, 2004
    Date of Patent: October 9, 2007
    Assignee: Avago Technologies General IP Pte Ltd
    Inventors: Michael A. Rencher, James R. Emmert
  • Patent number: 7280678
    Abstract: Methods and apparatus for pupil detection are described. First light is emitted from a first light source at a first illumination angle relative to the axis of a detector. Second light is emitted from a second light source at a second illumination angle relative to the axis. The first light and the second light can have substantially equal intensities. The second illumination angle is greater than the first illumination angle. Reflected first light and reflected second light are received at the detector. The difference between the reflected first light and the reflected second light can be determined. The difference can be used to detect the pupils of a subject's eyes.
    Type: Grant
    Filed: February 28, 2003
    Date of Patent: October 9, 2007
    Assignee: Avago Technologies General IP Pte Ltd
    Inventors: Richard Earl Haven, David James Anvar, Julie Elizabeth Fouquet, John Stewart Wenstrand
  • Patent number: 7279928
    Abstract: A programmable logic device (PLD) with logic blocks and an embedded array block includes an x-bit (xB)/y-bit (yB) coder programmed into the embedded array block instead of into the logic blocks. An xB/yB coder programmed into an embedded array block of a PLD instead of into logic blocks utilizes less space in a PLD than an xB/yB encoder programmed into the logic blocks. Additionally, the xB/yB coder can operate without row or column crossing for efficient timing in high-speed applications. In an embodiment, the xB/yB coder is an 8B/10B coder. In a further embodiment, the 8B/10B coder comprises a 5B/6B encoder and a 3B/4B encoder.
    Type: Grant
    Filed: October 4, 2005
    Date of Patent: October 9, 2007
    Assignee: Avago Technologies General IP Pte. Ltd
    Inventor: Mohit Arora
  • Patent number: 7276684
    Abstract: A photocell system includes a current control circuit that provides an offset voltage. Each photocell in a photocell array includes an opto-electrical converter receives the offset voltage such that the opto-electrical converter establishes a DC operating point. In one embodiment, each photocell includes the current control circuit. In an alternate embodiment, a single current control circuit provides the offset voltage for the entire photocell array.
    Type: Grant
    Filed: June 16, 2003
    Date of Patent: October 2, 2007
    Assignee: Avago Technologies General IP Pte Ltd
    Inventor: Brian James Misek
  • Patent number: 7276390
    Abstract: An InAsP active region for a long wavelength light emitting device and a method for growing the same are disclosed. In one embodiment, the method comprises placing a substrate in an organometallic vapor phase epitaxy (OMVPE) reactor, the substrate for supporting growth of an indium arsenide phosphide (InAsP) film, forming a quantum well layer of InAsP, and forming a barrier layer adjacent the quantum well layer, where the quantum well layer and the barrier layer are formed at a temperature of less than 520 degrees C. Forming the quantum well layer and the barrier layer at a temperature of less than 520 degrees C. results in fewer dislocations by suppressing relaxation of the layers. A long wavelength active region including InAsP quantum well layers and InGaP barrier layers is also disclosed.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: October 2, 2007
    Assignee: Avago Technologies General IP Pte Ltd
    Inventors: David P. Bour, Michael R. T. Tan, William H. Perez
  • Patent number: 7265488
    Abstract: A light emitting device in which a primary light generator, such as a light emitting diode (LED) or laser diode, is operable to emit a primary light that is received by a body of wavelength converting material. A portion of the primary light is absorbed by the body of wavelength converting material and is emitted as secondary light. The wavelength converting material contains phosphor nano-particles and larger phosphor particles. The phosphor nano-particles prevent transmission of primary light while the larger phosphor particles provide efficient light conversion.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: September 4, 2007
    Assignee: Avago Technologies General IP Pte. Ltd
    Inventors: Kee Yean Ng, Kheng Leng Tan, Tajul Arosh Baroky, Janet Bee Yin Chua, Kok Chin Pan
  • Patent number: 7253528
    Abstract: A design methodology reduces electromigration in integrated circuit joints such as flip-chip bumps by seeking to produce a more uniform current distribution at the interface between the integrated circuit pad and the joint while maintaining an interface form that coincides with standard integrated circuit designs is presented. The design methodology addresses the current distribution at the pad by introducing an intermediate trace routing design between the current delivering trace and the pad that distributes the inflow of current from the trace to multiple points of entry on the pad. The intermediate trace routing design includes an outer trace channel connected to the current delivering trace. A plurality of conductive trace leads connect the outer trace channel to the pad. Preferably, each of the plurality of conductive trace leads is characterized by a respective trace impedance so as to distribute equal current flow through each of the leads to the pad.
    Type: Grant
    Filed: February 1, 2005
    Date of Patent: August 7, 2007
    Assignee: Avago Technologies General IP Pte. Ltd.
    Inventors: Walter John Dauksher, Wayne Patrick Richling, William S. Graupp
  • Patent number: 7088397
    Abstract: A digital image capture system includes an image sensor, a package structure for holding the image sensor, and electrical connectors for creating electrical connections between the image sensor and a circuit board. The package structure includes attachment features that enable an optics system to be securely attached to the package structure after the package structure has been soldered to the circuit board In an embodiment, the attachment features align the optics system with the image sensor without having to power up the image sensor. An embodiment of the attachment features includes mechanical attachment features, such as clip arms and/or clip receivers. In an embodiment, the optics system includes attachment features that are complementary to the attachment features of the package structure. The package structure and optics system may additionally include complementary contact surfaces that create a light-tight connection between the optics system and the package structure.
    Type: Grant
    Filed: November 16, 2000
    Date of Patent: August 8, 2006
    Assignee: Avago Technologies General IP Pte. Ltd
    Inventors: Andrew Arthur Hunter, James-Yu Chang, Park-Kee Yu, Ray Schuder
  • Patent number: 7079973
    Abstract: An apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC) includes operating a clock associated with the IC at a frequency (fTARGET) at which IC operation is sought to be determined, measuring the actual clock period (TCLOCK_OUT) at a clock output, scan testing the IC, measuring the actual clock period (TSCAN_CLOCK_OUT) at the clock output, determining a delay by calculating the difference between TSCAN_CLOCK_OUT and TOLOCK_OUT, and compensating for the delay by increasing the clock frequency during scan test.
    Type: Grant
    Filed: April 6, 2004
    Date of Patent: July 18, 2006
    Assignee: Avago Technologies General IP Pte. Ltd.
    Inventors: Richard S. Rodgers, Jeffrey R. Rearick, Cory D. Groth
  • Patent number: 7072590
    Abstract: In one aspect, the invention features a fiber optic receiver that includes a preamplifier circuit incorporated together with an opto-electronic transducer in a receiver optical sub-assembly (ROSA), and an adjustable bandwidth post-amplifier that is located outside the ROSA to allow the overall size of the receiver package to be reduced. The ROSA is mounted on a substrate and is fitted with a fiber optic connector for coupling to a mating connector of a fiber optic cable. The opto-electronic transducer is incorporated within the ROSA and is configured to generate an electrical data signal in response to a received optical data signal. The preamplifier circuit is incorporated within the ROSA and is operable to linearly amplify an electrical data signal generated by the opto-electronic transducer. The adjustable bandwidth post-amplifier circuit is mounted on the substrate and is coupled to an output of the preamplifier circuit.
    Type: Grant
    Filed: March 26, 2001
    Date of Patent: July 4, 2006
    Assignee: Avago Technologies General IP Pte. Ltd.
    Inventors: Michael A. Robinson, Charles Graeme Ritchie, Peter H Mahowald
  • Patent number: 7058053
    Abstract: A method to process a multicast transfer request within an interconnect device includes receiving the multicast transfer request pertaining to a packet stored by the interconnect device. A number of unicast transfer requests are spawned based on the multicast transfer request. Responsive to a generation of a transfer grant for at least one of the number of unicast transfer requests, a determination is made whether transfer grants have been generated for all of the number of unicast transfer requests. If so, then the packet stored by the interconnect device, and to which the multicast transfer request pertains, is discarded.
    Type: Grant
    Filed: October 12, 2001
    Date of Patent: June 6, 2006
    Assignee: Avago Technologies General IP PTE. Ltd.
    Inventor: Richard L. Schober
  • Patent number: 7057425
    Abstract: In one disclosed method, a dynamic signal is driven onto a driven end of a first signal line, and an ungrounded bias signal is driven onto a driven end of a second signal line. The ungrounded bias signal is then received at a receiving end of the second signal line, and the dynamic signal is received at a receiving end of the first signal line. The receiving end of the second signal line is coupled to a first input of a quasi-differential receiver, and the receiving end of the first signal line is coupled to a second input of the receiver. The ungrounded bias signal is used to bias a toggle point of the receiver, and the dynamic signal is used to toggle an output of the receiver. Variations of this method, and apparatus that can perform this and other methods, are also disclosed.
    Type: Grant
    Filed: May 25, 2004
    Date of Patent: June 6, 2006
    Assignee: Avago Technologies General IP Pte. Ltd.
    Inventors: David D. Balhiser, Jason Todd Gentry
  • Patent number: 7053651
    Abstract: A CMOS switching circuit that includes a charge reservoir and a multiplexer connected to the charge reservoir. The multiplexer receives control signals from a delay line and a control signal line, and it delivers a switching signal to an output terminal. A first set of signals delivered to the control terminals of the multiplexer causes the charge reservoir to deliver charge to the output terminal, and a second set of signals delivered to the control terminals causes charging of the charge reservoir. With the charge reservoir, charge from falling signals is conserved and used to help rising signals at the output, reducing the power required to provide an output switching signal.
    Type: Grant
    Filed: September 15, 2004
    Date of Patent: May 30, 2006
    Assignee: Avago Technologies General IP Pte. Ltd.
    Inventor: Jason Gonzalez
  • Patent number: 7054356
    Abstract: A method and apparatus for testing a serial connection is presented. A serial data stream is transmitted from a sending device to a receiving device. The serial data stream is generated using sending device timing information and input data. A receiver in the receiving device recovers both the timing information and the input data and then inputs them back into a transmitter located in the receiving device. The transmitter in the receiving device then generates a second serial data stream based on the recovered input data and the sending device timing information. A receiver in the sending device receives the second serial data stream and outputs the sending device timing information and input data to a FIFO buffer, for alignment of the input data. Since the input data and timing information are generated based on a sending device timing information, the FIFO can provide a signal for testing by performing phase alignment on the data. There is no need to re-synchronize the data in the sending device.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: May 30, 2006
    Assignee: Avago Technologies General IP Pte. Ltd.
    Inventor: Mark A Wahl
  • Patent number: 7053728
    Abstract: An impedance transformation network, power amplifier and method for efficiently transmitting an output signal utilizes a series varactor device to provide a variable impedance transformation. The series varactor device may include a number of stacked ferroelectric varactors that function as a variable capacitor to provide the variable impedance transformation in response to the power level of the output signal.
    Type: Grant
    Filed: March 19, 2004
    Date of Patent: May 30, 2006
    Assignee: Avago Technologies General IP Pte. Ltd.
    Inventor: Chul Hong Park