Patents Assigned to Avago Technologies General IP (Singapore) Pte. Ltd.
  • Patent number: 10123371
    Abstract: The present disclosure is directed to methods and system for managing communication of packets. A transceiver node receives a plurality of IP data packets from an internet protocol (IP) network. The transceiver node separates the IP data packets into a first set and a second set of IP data packets, according to channel conditions of a cellular network and a wireless local area network (WLAN). The transceiver node transmits, to a user device, the first set of IP data packets using a cellular network protocol of the cellular network and the second set of IP data packets using a WLAN protocol of the WLAN, causing the user device to aggregate the first set of IP data packets transmitted using the cellular network protocol with the second set of IP data packets transmitted using the WLAN protocol.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: November 6, 2018
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Yong Li, Shuval Polacheck, Florin Baboescu
  • Publication number: 20180316950
    Abstract: A system controls a transmission of a sequence of compressed video data from an encoder buffer to a network for delivery to a decoder buffer. Control of the transmission includes to: determine characteristics of a video transmission path between the encoder buffer and the decoder buffer, the characteristics comprising at least one of a buffer size of the decoder buffer, an input rate of the decoder buffer, and a buffer size of an equivalent intermediary buffer of the video transmission path; determine a transmission rate from the characteristics of the video transmission path and from the sequence of compressed video data, the transmission rate being determined such that a target quality of service value can be guaranteed for the entire sequence of compressed video data transmitted at the determined transmission rate to the decoder buffer; and control transmission of the sequence of compressed video data at the determined transmission rate.
    Type: Application
    Filed: June 20, 2018
    Publication date: November 1, 2018
    Applicant: AVAGO TECHNOLOGIES GENERAL IP (Singapore) PTE. LTD.
    Inventors: Xuemin Chen, Yong Li
  • Publication number: 20180317149
    Abstract: Systems and methods of handling satellite channel and LTE coexistence are provided. A first device can identify at least one first frequency band. The first device can determine that at least one second frequency band of a plurality of second frequency bands overlaps with the at least one first frequency band. In response to determining that the at least one second frequency band overlaps with the at least one first frequency band, the first device transmits a message including an identifier of the first device and an indication of the at least one second frequency band to a second device. The second device receives the message. The second device, in response to receiving a channel request from the first device, allocates, from the plurality of second frequency bands, a second frequency band different from the at least one second frequency band.
    Type: Application
    Filed: June 29, 2018
    Publication date: November 1, 2018
    Applicant: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. .LTD.
    Inventors: Walid Nabhane, Xiaoxin Qiu, Jason C. Demas, Pascal G. Finkenbeiner
  • Publication number: 20180316540
    Abstract: In some aspects, the disclosure is directed to methods and systems for receive-side distortion cancellation in orthogonal frequency division multiplexing (OFDM). Each of a plurality of OFDM receivers generates a distortion signal; modulates, amplifies, and demodulates the distortion signal; and then mixes a received signal with an inverse of the demodulated distortion signal, along with demodulated distortion signals provided by each other receiver. The resulting output signal may be de-mapped and decoded, with amplifier distortion reduced.
    Type: Application
    Filed: April 24, 2018
    Publication date: November 1, 2018
    Applicant: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventor: Ba-Zhong SHEN
  • Patent number: 10115821
    Abstract: Semiconductor devices are provided that use both silicon on insulator region and bulk region of a fully depleted silicon on insulator (FDSOI) device. For example, a semiconductor device includes a drain region that is disposed above a first type well and a first drain extension region that is disposed above the first type well and laterally spaced apart from the drain region. The semiconductor device further includes a second drain extension region that is disposed above the first type well and is laterally spaced apart from the drain region and the first drain extension region. The semiconductor device further includes a source region disposed above a second type well and laterally spaced apart from the second drain extension.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: October 30, 2018
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Shom Ponoth, Akira Ito, Qing Liu
  • Patent number: 10112558
    Abstract: System, method and apparatus for one-pair power over Ethernet in an automotive application. In one embodiment, a power sourcing equipment transmits a forward path current to a powered device via a single conductor pair and receives a return path current from the powered device via a chassis of an automotive vehicle.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: October 30, 2018
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Sesha Thalpasai Panguluri, Minh Tran, James Yu, Wael William Diab
  • Publication number: 20180309455
    Abstract: Adaptive clocking schemes for synchronized on-chip functional blocks are provided. The clocking schemes enable synchronous clocking which can be adapted according to changes in signal path propagation delay due temperature, process, and voltage variations, for example. In embodiments, the clocking schemes allow for the capacity utilization of a logic path to be increased.
    Type: Application
    Filed: June 25, 2018
    Publication date: October 25, 2018
    Applicant: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Paul PENZES, Mark FULLERTON
  • Publication number: 20180308791
    Abstract: Semiconductor devices and manufacturing methods are provided for using a Recon interposer that provides a high density interface between the active semiconductor die and the semiconductor substrate and also provides the pitch fan-out. For example, a circuit assembly includes a silicon pad layer including a plurality of metal pads, each metal pad configured to receive a corresponding bump of a plurality of bumps. The circuit assembly further includes an oxide layer disposed on the silicon pad layer and an interposer dielectric layer disposed on the oxide layer. The interposer dielectric layer includes a plurality of routing traces that connect a top surface of the redistribution layer to a bottom surface of the interposer dielectric layer.
    Type: Application
    Filed: June 25, 2018
    Publication date: October 25, 2018
    Applicant: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Sam Ziqun ZHAO, Sam Komarapalayam KARIKALAN, Edward LAW, Rezaur Rahman KHAN, Pieter VORENKAMP
  • Publication number: 20180308841
    Abstract: A FinFET semiconductor device having semiconductor body including a source region of a first type, and a drain region of a second type, and a drain-region shallow trench isolation (STI) disposed in the drain region. The device includes a plurality of fins attached to the semiconductor body and extending across the semiconductor body, a channel gate disposed over a section of the plurality of fins; a supplemental gate disposed on the drain-region STI.
    Type: Application
    Filed: April 24, 2017
    Publication date: October 25, 2018
    Applicant: Avago Technologies General IP (Singapore) Pte. Ltd
    Inventors: Qing LIU, Akira ITO
  • Patent number: 10108359
    Abstract: A system and method for efficient cache buffering are provided. The disclosed method includes receiving a host command from a host, extracting command information from the host command, determining an Input/Output (I/O) action to be taken in connection with the host command, determining that the I/O action spans more than one strip, and based on the I/O action spanning more than one strip, allocating a cache frame anchor for a row on-demand along with a cache frame anchor for a strip to accommodate the I/O action.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: October 23, 2018
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Horia Simionescu, Timothy Hoglund, Sridhar Rao Veerla, Panthini Pandit, Gowrisankar Radhakrishnan
  • Patent number: 10109364
    Abstract: A non-volatile memory cell, having an antifuse for storing data, is disclosed for use in a non-volatile data storage device. The non-volatile memory cell includes multiple redundant signal pathways to provide redundant access to the antifuse. During operation, the non-volatile memory cell can access the antifuse using a first signal pathway from among the multiple redundant signal pathways. However, when the first signal pathway is inoperable, the non-volatile memory cell is able to access the antifuse using a second signal pathway from among the multiple redundant signal pathways. The non-volatile memory cell is fabricated using a continuous region of one or more diffusion layers to allow efficient connection to other non-volatile memory cells to form an array of memory cells for the non-volatile data storage device.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: October 23, 2018
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Jonathan A. Schmitt, Jermyn Tseng
  • Patent number: 10108489
    Abstract: Embodiments are related to systems and methods for data storage, and more particularly to systems and methods for storing and accessing data from a flash memory.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: October 23, 2018
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Zhijun Zhao, Shaohua Yang, Victor Krachkovsky
  • Patent number: 10110677
    Abstract: A context-aware decision making system may include at least one processor circuit that is configured to obtain an environmental profile of an environment associated with a user. The at least one processor circuit is configured to determine a predicted behavior of the user based at least on the obtained environmental profile. The at least one processor circuit may be configured to determine the predicted behavior of the user using at least one predictive model associated with the user. The at least one processor circuit may be configured to perform an action related to the predicted behavior of the user, such as an action that facilitates the predicted behavior of the user, an action that impedes the predicted behavior of the user, and/or an action that provides information related to the predicted behavior of the user.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: October 23, 2018
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Jeyhan Karaoguz, Marcus Christopher Kellerman, John Stuart Walley, James Duane Bennett, Xuemin Chen, Bradley Donald Blanche
  • Patent number: 10108576
    Abstract: Systems and methods provide zone management for devices in a Serial Attached Small Computer System Interface (SAS) topology. In one embodiment, a zone management device stores a zone map that identifies an initial zone of a device in the topology. The management device detects changes in the topology, and identifies a current zone of the device subsequent to the change in the topology. The management device compares the zone map for the device to the current zone to identify a change in the zone of the device, and generates a message for an expander in the topology based on the change in the zone. The management device then transmits the message to the expander to restore the zone of the device to the initial zone.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: October 23, 2018
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Benjamin Knoblauch, Charles D. Henry, Jason A. Unrein
  • Patent number: 10111071
    Abstract: A system for facilitating communications in a mesh network is provided. One or more devices of the mesh network may participate as routing nodes to provide range extension for any other devices in the mesh network that would otherwise be out of range from one another. In one or more implementations, Bluetooth Low Energy (BLE) may be used as the physical transport of the mesh network.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: October 23, 2018
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Angel Polo, Guoxin Xie, David Hsu, Khan M. Muneer, Xin Tian, Wenbin Yu, Victor G. Zhodzishsky
  • Publication number: 20180302735
    Abstract: Methods, systems, and apparatuses are described for determining relative locations of wireless loudspeakers and performing channel mapping thereof. An audio processing component utilizes sounds produced by wireless loudspeakers during setup/installation procedures, which are received by a microphone at locations in an acoustic space, to determine an amount of time between when the audio signal is initially transmitted and when the microphone signal is received. The audio processing component also utilizes wireless timing signals provided by a wireless transceiver, at locations in the acoustic space, to wireless loudspeakers and then back to the wireless transceiver to determine an amount of time between transmission and reception by the wireless transceiver. The timing delays are used to determine the locations of the wireless loudspeakers in the acoustic space.
    Type: Application
    Filed: June 18, 2018
    Publication date: October 18, 2018
    Applicant: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: James Dougherty, Juin-Hwey Chen
  • Patent number: 10102168
    Abstract: A device implementing a scalable low-latency mesh may include a memory management unit, an egress processor, and an egress cell circuit that includes at least a first queue and a second queue. The memory management unit may be configured to buffer first cells for transmission. The egress cell circuit may be configured to queue the first cells from the memory management unit in the first queue, queue second cells from an off-chip memory management unit of another device in the second queue, and schedule the first cells from the first queue and second cells from the second queue for transmission via an egress processor. The egress processor may be configured to transmit the first and second cells over at least one first port.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: October 16, 2018
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Surendra Anubolu, Mohan Venkatachar Kalkunte
  • Patent number: 10103957
    Abstract: A method of managing traffic in a communications channel includes the steps of receiving a subscriber ID corresponding to a subscriber, performing a spectral analysis on a signal received from the subscriber within a time interval identified by the subscriber ID, and adjusting transmission characteristics of the subscriber based on the spectral analysis.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: October 16, 2018
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Jonathan S. Min, Fang Lu, Bruce J. Currivan, Kevin Eddy
  • Publication number: 20180295444
    Abstract: Provided are communication devices having adaptable features and methods for implementation. One device includes at least one adaptable component and a processor configured to detect an external cue relevant to operation of the at least one adaptable component, to determine a desired state for the at least one adaptable component corresponding to the external cue, and then to dynamically adapt the at least one adaptable component to substantially produce the desired state. One adaptable component comprises at least one adaptable speaker system. Another adaptable component comprises at least one adaptable antenna.
    Type: Application
    Filed: June 12, 2018
    Publication date: October 11, 2018
    Applicant: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventor: John WALLEY
  • Publication number: 20180294798
    Abstract: A non-linear impedance terminates a transmission line. The non-linear impedance may be implemented with a back-to-back connected inverter pair. The pair acts as a non-linear resistor. A process, voltage, temperature (PVT) tracking circuit may also be provided to improve PVT tracking, with resistance of transistors locked to a calibrated resistor. The replica circuit does not appear in the signal path, and does not add capacitive load.
    Type: Application
    Filed: June 11, 2018
    Publication date: October 11, 2018
    Applicant: Avago Technologies General IP (Singapore) Pte. Ltd .
    Inventors: Guansheng Li, Jun Cao