Abstract: The present application relates generally to silicon photomultiplier (SiPM) detector arrays. In one aspect, there is a system including an array of cells each including a single-photon avalanche diode (SPAD) reverse-biased above a breakdown voltage of the SPAD. The system may further include a trigger network configured to generate pulses on a trigger line in response to SPADs of the array undergoing breakdown. The system may still further include a pulse-width filter configured to block pulses on the trigger line whose pulse width is less than a threshold width.

Abstract: Packets in a data communications network are encapsulated by an encapsulation module on a sending computer and decapsulated on the receiver computer, the transmission of data packets being controlled by credit sent by the receiving computer to avoid causing congestion. The encapsulation module varies fields in the packets that are used by switches to determine the path to the destination, so as to distribute the load of a transfer across a plurality of paths to the receiving computer. The sending and receiving computers use per path packet delivery, loss, latency and packet trimming information to detect abnormal network behavior and submit alerts and summary statistics to a monitoring station. The monitoring station uses this information to detect network bottlenecks and other faults and to localize them to specific switches or links.

Abstract: Various embodiments of the present disclosure improve existing multi-layer and other network technologies by routing and processing client requests that require machine learning based on the machine learning capabilities of each network device and/or other computer resource characteristics of different network devices. This ensures that network latency and throughput, among other computer resource consumption characteristics, will be improved as machine learning processing can occur at the most suitable network device or be distributed among various suitable network devices.

Abstract: Systems and methods of communicating use device level throttling. Some embodiments relate to a method of communicating in a network. The systems and methods can provide a first communication associated with a device for issuance, issue the first communication if a queue depth value for the device is less than an issued communication value, and listing the first communication on a pend list for the device if a queue depth value for the device is less than the issued communication value.

Abstract: In some aspects, the disclosure is directed to methods and systems for reducing memory utilization and increasing efficiency during affine merge mode for versatile video coding by utilizing motion vectors stored in a motion data line buffer for a prediction unit of a second coding tree unit neighboring a first coding tree unit to derive control point motion vectors for the first coding tree unit.

Abstract: A system includes a first circuit configured to provide a digitally pre-distorted input signal, a digital-to-analog converter including a number of unit elements, a digital input, and a digital output. Each unit element is configured to receive a reference voltage and to be controllable by a control signal provided in response to the digitally pre-distorted input signal. The digital-to-analog converter provides an analog output. The first circuit is configured to reduce distortion due to signal dependent changes to the reference voltage. The signal dependent changes can be due at least in part to current through the supply network that supplies the reference voltage. The digital to analog converter can be a voltage mode converter.

Abstract: System, method and computer-readable storage medium including a first communications device including a host processor to wake up upon receipt of a message and stream audio directly to another device via wireless communication, a second communications device including circuitry to control the streaming of the audio by sending messages to the first communications device and to control a display. The host processor of the first communications device enters a sleep state during audio streaming while a state of the display is off. Reduction in the number of messages sent by the second communications device, or offloading of message handling by the host processor, allows the host processor to remain in a sleep state for longer periods.

Abstract: Described herein are systems, methods, and products utilizing a cache coherent switch on chip. The cache coherent switch on chip may utilize Compute Express Link (CXL) interconnect open standard and allow for multi-host access and the sharing of resources. The cache coherent switch on chip provides for resource sharing between components while independent of a system processor, removing the system processor as a bottleneck. Cache coherent switch on chip may further allow for cache coherency between various different components. Thus, for example, memories, accelerators, and/or other components within the disclose systems may each maintain caches, and the systems and techniques described herein allow for cache coherency between the different components of the system with minimal latency.

Abstract: A semiconductor chip with error detection and correction includes multiple pipes and each pipe is coupled to one or more ports on the semiconductor chip. The semiconductor chip further includes a state machine coupled to the pipes to generate a number of events consisting of read- and/or scan-type events associated with a plurality of storage elements. The state machine is implemented in hardware and can centrally detect and correct erroneous memory entries across the plurality of storage elements.

Abstract: An apparatus includes an ingress data buffer, an ingress processor, an egress processor, and a recirculation data buffer. The apparatus is configured to provide unified packet recirculation via the recirculation data buffer and a single recirculation port on the ingress data buffer. The apparatus can be a switch, router or other network device.

Abstract: A semiconductor chip for implementing load-aware equal-cost multipath routing includes a number of ports and several pipes, each pipe being coupled to a portion of ports on the semiconductor chip, and a central unit consisting of a state machine and multiple databases. The databases contain information regarding a communication network including an overlay network and an underlay network, and the state machine is implemented in hardware and can determine at least one feature of the overlay network and a corresponding group of paths within the underlay network.

Abstract: Described herein are systems and methods related to a converter includes a number of unit cells. The unit cells each include a first transistor and a second transistor. The first transistor is coupled in series with an output of the unit cell, and the second transistor is configured to have a capacitive characteristic that reduces a non-linear capacitive characteristic of the first transistor. The converter can be a voltage or current mode digital to analog converter.

Abstract: Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). The SAR ADC includes a sample and digital to analog conversion (DAC) circuit configured to sample an input voltage, a comparator circuit coupled to the sample and DAC circuit and having an output, a first set of storage circuits, and a comparator driver. The comparator driver is disposed between the output and the first set of storage circuits (e.g., ratioed latched. The first set of storage circuits are coupled to the comparator circuit and the sample and DAC circuit. The comparator driver can include a first driver and second driver. The first driver is coupled to a first input of a first storage circuit of the first set of storage circuits, and the second driver is coupled to first inputs of a second set of storage circuits within the first set of storage circuits.

Abstract: A wireless communication device (alternatively, device, WDEV, etc.) includes at least one processing circuitry configured to support communications with other WDEV(s) and to generate and process signals for such communications. In one example, the circuitry is configured to generate a null data packet (NDP), transmit at least a portion of the NDP to another wireless communication device via fewer than all of a plurality of sub-channels of a communication channel, and receive feedback from the another wireless communication device that is based on the another wireless communication processing the at least the portion of the NDP that is received via the fewer than all of the plurality of sub-channels of the communication channel. In one example, the generated NDP includes at least one signal field (SIG) field therein that includes information to specify a preamble puncturing option or the information is transmitted in a previous packet.

Abstract: The method includes providing at least one bit in an extended capability information element of a beacon frame or a probe response frame used during association of an access point and a station. The at least one bit indicates availability or unavailability of the access point to provide service to the station. The method also includes receiving the beacon frame or the probe response frame and cancelling the association in response to the at least one bit indicating the unavailability of the access point to provide the service to the station.

Abstract: Disclosed herein are related to systems and methods for a successive approximation analog to digital converter (SAR ADC). In one aspect, the SAR ADC includes a calibration circuit configured to receive some or all of the plurality of bits corresponding to the input voltage and accumulates or averages at least some of the bits corresponding to the input voltage. The calibration circuit is configured to provide a first offset signal to control a first offset associated with a first comparator, a second offset signal to control a second offset associated with a second comparator, or reduce an offset difference associated with the first offset and the second offset.

Abstract: A device includes integer multiplier circuits, a multiplexer circuit configured to provide portions of mantissas of a set of first data elements having a floating-point data type and portions of mantissas of a set of second data elements having the floating-point data type to respective integer multiplier circuits, wherein each integer multiplier circuit is configured to multiply a respective portion of the mantissa of a first data element by a respective portion of the mantissa of a second data element to generate a partial product. The device further includes output circuits configured to generate an output data element based on the partial products generated by the integer multiplier circuits and exponents of the set of first data elements and of the set of second data elements.

Abstract: Embodiments of systems and methods for wireless communication in a wireless network include generation of a bandwidth query report poll (BQRP) frame by an access point and transmission of the BQRP frame to multiple wireless stations. The BQRP frame includes a bandwidth query for each station. Each wireless station receives the BQRP frame and generates a bandwidth query report. The bandwidth query report includes channel availability information at a corresponding wireless station. The access point allocates channel resources to each wireless station according to the channel availability information.

Abstract: An apparatus may include a first clock generator configured to receive an input clock signal, and generate two or more first-level clock signals of a track-and-hold circuit, a phase interpolator configured to generate an interpolated clock signals, wherein the interpolated clock signal is based on the two or more first-level clock signals, and a second clock generator configured to generate two or more second-level clock signals based on the interpolated clock signal, wherein the phase of the two or more second-level clock signals relative to the phase of a respective first-level clock signal is determined, at least in part, by the phase of the interpolated clock signal.

Abstract: A video decoder is provided that includes memory and a processor coupled to the memory. The processor may be configured to convert a bitstream into inter-prediction parameters and reconstruct motion data based on the inter-prediction parameters. The processor may further be configured to refine the motion data based on finding a match between a current template of a current picture and a reference template of a reference picture and perform a motion compensation operation with the refined motion data and a reference block to generate an inter-prediction block. The processor may be configured to add the inter-prediction block to an inter-residual block to produce a reconstructed block. The motion data may be reconstructed without refined motion data associated with a previous prediction unit.