Patents Assigned to Avago Technologies International Sales Pte. Limited
  • Patent number: 10977201
    Abstract: A bridge device tracks each individual IO between two PCIe busses and provides a translated address based on a scatter/gather list. Tracking provides a natural means of scatter/gather list translation to and from a native PCIe storage protocol's scatter/gather list (or other scatter/gather like mechanism). In addition, the awareness of the IO context provides a means for detecting erroneous transactions that would otherwise cause a system error and/or data corruption to be aborted preventing those error scenarios.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: April 13, 2021
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Luke E. McKay, Roger T. Clegg
  • Patent number: 10971450
    Abstract: Hexagonally arranged connection patterns for device packaging allow high density circuitry dies to be assembled into packages of manufacturable size. The connection patterns may be patterns for solder ball arrays or other types of connection mechanisms under a semiconductor package. Despite the increased density of the connection patterns, the connection patterns meet the demanding crosstalk specifications for high speed operation of the high density circuitry.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: April 6, 2021
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Arun Ramakrishnan, Reza Sharifi, Dharmendra Saraswat
  • Patent number: 10971622
    Abstract: A transistor structure includes a substrate and a fin structure on the substrate. The fin structure includes an undoped portion, a first doped portion, and a second doped portion. The transistor structure includes an electrode on the fin structure between the first doped portion and the second doped portion, and an insulating layer on the fin structure. The transistor structure includes a first trench in the insulating layer at a first side of the fin structure and between the electrode and the second doped portion, and a second trench in the insulating layer at a second side of the fin structure and between the electrode and the second doped portion. The first trench includes a first conductive material, and the second trench includes a second conductive material.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: April 6, 2021
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Qing Liu, Akira Ito
  • Patent number: 10971954
    Abstract: Systems and methods for object detection are provided. The system includes at least a coil, a small signal generator, a small signal receiver, and a processor. The small signal generator includes a digital-to-analog converter circuit with programmable impedance. The small signal generator is configured to select an output impedance for the digital-to-analog circuit for capacitive sensing or radio-frequency identification (RFID) tag detection; generate a small signal according to the output impedance; and provide the small signal to the coil. The small signal receiver receives the small signal and a response signal associated with the small signal and measures the response signal to generate a measured signal. The processor compares the measured signal with one or more reference signals and performs capacitive sensing and/or detect a RFID tag according to the comparison.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: April 6, 2021
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Yongjie Jiang, Mark Rutherford, John Walley
  • Patent number: 10971643
    Abstract: A semiconductor device, sensor, and array of SPAD cubes are described. One example of the disclosed semiconductor device includes an array of single-photon avalanche diodes, each single-photon avalanche diode including an undepleted anode region, an undepleted cathode region, an active depleted region positioned between the anode region and cathode region, and at least one conductive trench extending between the anode region and cathode region. In some examples, the at least one conductive trench surrounds the active depleted region and reflects light back into the active depleted region such that one or more photons can be absorbed within the active depleted region even though an absorption coefficient of the light is greater than a thickness of the active depleted region.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: April 6, 2021
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventor: Claudio Piemonte
  • Patent number: 10965951
    Abstract: A pipeline video decoder with memory latency management includes memory and at least one processor coupled to the memory. The processor converts a received bitstream into symbol data including pixel data and intra-prediction and inter-prediction control parameters. The processor generates decoder-pipeline region (DPR)-based coarse motion data based on the inter-prediction control parameters. The processor further fetches one or more reference blocks associated with a current prediction unit (PU) of a DPR based on the coarse motion data, and generates decoded motion data based on the inter-prediction control parameters and refined motion data. The refined motion data is generated based on the decoded motion data and the one or more reference blocks.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: March 30, 2021
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventor: Minhua Zhou
  • Patent number: 10966074
    Abstract: A power-efficient, balanced, and reliable true wireless Bluetooth stereo audio solution is provided. Two audio sink devices are used to render audio content received from an audio source. One sink device is connected to the audio source via a primary link. The other sink device sniffs communication on the primary link. The two sink devices are connected via a hybrid link. In some embodiments, a token is passed dynamically between the two sink devices. The sink device that has the token acts as a primary sink device on a primary link with the source. The other sink device acts as a slave to the primary link.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: March 30, 2021
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Xianbo Chen, Chikan Kwan, Shawn Ding
  • Patent number: 10966161
    Abstract: In some aspects, the disclosure is directed to methods and systems for in-packet transmission power control. Measurement circuitry in communication with a transmission stage of a device is configured to generate a transmitted signal strength measurement signal based on an output of the transmission power amplifier during transmission of a packet. Measurement conversion circuitry connected to the measurement circuitry is configured to convert the transmitted signal strength measurement signal from the measurement circuitry to an output power measurement. Power control circuitry connected to the measurement conversion circuitry is configured to generate a power correction signal based on the output power measurement and an output power target value. Power ramping circuitry connected to the power control circuitry is configured to provide a gain signal to the transmission stage of the device based on the power correction signal.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: March 30, 2021
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Mohamed Abou Bakr Othman, Thomas Baker, Vincent Roussel, Federico Cattivelli
  • Patent number: 10943340
    Abstract: An apparatus for combining multiple images to form a blended image, configured to identify regions of overlap: (i) in a first image and in a second image, corresponding to where those first and second images will overlap each other in the blended image; and (ii) in the first image and in a third image, corresponding to where those first and third images will overlap each other in the blended image, identify an image quality associated with each region of overlap, determine a gain for each image that, when applied to the image as a whole, will minimise a sum of: (i) a difference between the image qualities associated with the regions of overlap in the first and second images; and (ii) a difference between the image qualities associated with the regions of overlap in the first and third images and apply the respective gains to the first, second and third images.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: March 9, 2021
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: James Hutchinson, Thomas Oscar Miller, Stephen John Barlow, Jack Stuart Haughton
  • Patent number: 10944518
    Abstract: A wireless communication device (alternatively, device, WDEV, etc.) includes at least one processing circuitry configured to support communications with other WDEV(s) and to generate and process signals for such communications. In some examples, the device includes a communication interface and a processing circuitry, among other possible circuitries, components, elements, etc. to support communications with other WDEV(s) and to generate and process signals for such communications. The WDEV generate a first orthogonal frequency division multiple access (OFDMA) frame that specifies information regarding resource unit (RUs) to be used by other WDEV. The WDEV transmits the first OFDMA frame to other WDEVs and receives a second OFDMA frame from the WDEVs based on some RUs specified within the first OFDMA frame. The WDEV then generates and transmits a third OFDMA frame to the other WDEVs (e.g., based on RU(s) spanning RU(s) within which information is received in the second OFDMA frame).
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: March 9, 2021
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Zhou Lan, Matthew James Fischer
  • Patent number: 10944432
    Abstract: An interleaved encoder includes a number of encoders consisting of L parallel encoders, and a first switch circuit to sequentially couple an input node to an input port of one of the encoders. The input node receives a group of K*L symbols. Each symbol of the group of K*L symbols is received in synch with a respective clock pulse of a group of K*L clock pulses. The first switch circuit is synched with clock pulses of the group of K*L clock pulses, and sequentially couples the input node to an input port of a subsequent one of the encoders in response to each clock pulse of the group of K*L clock pulses.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: March 9, 2021
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Chungming Tu, Thomas V. Souvignier, Ahmad Darabiha
  • Patent number: 10938444
    Abstract: A full duplex repeater includes an upstream echo canceller and noise reduction circuitry. The noise reduction circuitry is configured to receive an upstream signal from the upstream echo canceller, separate the upstream signal into a plurality of Fast Fourier Transform (FFT) blocks, multiply the upstream signal by a 100% raised cosine window, convert the upstream signal into frequency domain using FFT, clean predetermined portions of the upstream signal in the FFT blocks based on a predetermined threshold, convert the upstream signal from frequency domain to time domain using Inverse FFT; and recombine the FFT blocks.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: March 2, 2021
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventors: Avraham Kliger, Anatoli Shindler, Yitshak Ohana
  • Patent number: 10935639
    Abstract: Systems and circuits directed to a time-of-flight measurement system are provided. More specifically, an illustrative optical sensor is disclosed to include a plurality of avalanche photodiodes, at least one of the plurality of avalanche photodiodes being in communication with amplifier common node through an impedance converter that is responsive to a control signal and selectively connects or disconnects the at least one avalanche photodiode from the common node based on the control signal. In an example, the impedance converter is also configured to preserve current generated from the at least one avalanche photodiode.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: March 2, 2021
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventors: Milos Davidovic, Reinhard Enne, Gunther Leopold Steinle
  • Patent number: 10931573
    Abstract: A Layer 2 network switch is partitionable into a plurality of switch fabrics. The single-chassis switch is partitionable into a plurality of logical switches, each associated with one of the virtual fabrics. The logical switches behave as complete and self-contained switches. A logical switch fabric can span multiple single-chassis switch chassis. Logical switches are connected by inter-switch links that can be either dedicated single-chassis links or logical links. An extended inter-switch link can be used to transport traffic for one or more logical inter-switch links. Physical ports of the chassis are assigned to logical switches and are managed by the logical switch. Legacy switches that are not partitionable into logical switches can serve as transit switches between two logical switches.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: February 23, 2021
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventors: Sathish Kumar Gnanasekaran, Badrinath Kollu, Richard L. Hammons, Ramkumar Vadivelu, Dan Norbert Retter, Jianqiang Zhou, Ponpandiaraj Rajarathinam, Daniel Ji Yong Park Chung
  • Patent number: 10931288
    Abstract: Disclosed herein are embodiments of an apparatus and a method for generating a quadrature clock signal. In one aspect, the apparatus includes a first delay circuitry to delay a clock signal according to a first control signal to generate a first delayed clock signal. In one aspect, the apparatus includes a second delay circuitry to delay the clock signal according to a second control signal to generate a second delayed clock signal. In one aspect, the apparatus includes a delay controller forming a first feedback loop with the first delay circuitry, and forming a second feedback loop with the second delay circuitry, where the delay controller determines a difference between the first delayed clock signal and the second delayed clock signal and modifies the first control signal and the second control signal according to the determined difference.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: February 23, 2021
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Zhiyu Ru, Tim Yee He, Siavash Fallahi, Ali Nazemi, Delong Cui, Jun Cao
  • Patent number: 10932262
    Abstract: A device implementing unified coordination of wireless communications over multiple physical layers may include a MAC module communicatively coupled to first and second physical layer modules that are each configured to communicate with another device over first and second physical wireless channels, respectively. The MAC module may be configured to provide data to the first physical layer module for transmission to the another device over the first physical wireless channel, where the first physical wireless channel is associated with a first link parameter. The MAC module may be further configured to facilitate initializing the second physical wireless channel based at least in part on the first link parameter of the first physical wireless channel, and after initialization of the second physical wireless channel, provide second data to the second physical layer module for transmission to the another device over the second physical wireless channel.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: February 23, 2021
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventors: Vinko Erceg, Mark Gonikberg, Rohit Gaikwad, Hongyu Xie, Anand Iyer, Venkat Kodavati, Tirdad Sowlati, Payam Torab Jahromi, Matthew J. Fischer
  • Patent number: 10922848
    Abstract: A device implementing the subject pixel storage for graphical frame buffers may include at least one processor configured to obtain a plurality of data units containing a plurality of pixels stored in memory, each of the plurality of data units including a first pixel of the plurality of pixels packed in succession with at least a portion of a second pixel of the plurality of pixels, in which the plurality of pixels is represented by a number of bits, obtain a group of pixels from the plurality of pixels, and store the group of pixels using a targeted number of bits. A method and computer program product implementing the subject pixel storage for graphical frame buffers is also provided.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: February 16, 2021
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventors: Richard Hayden Wyman, Brian Francis Schoner, David Chao Hua Wu, Timothy James Mamtora
  • Patent number: 10924333
    Abstract: One embodiment of the present invention provides a switch system. The switch includes a port that couples to a server hosting a number of virtual machines. The switch also includes a link tracking module. During operation, the link tracking module determines that reachability to at least one end host coupled to a virtual cluster switch of which the switch is a member is disrupted. The link tracking module then determines that at least one virtual machine coupled to the port is affected by the disrupted reachability, and communicates to the server hosting the affected virtual machine about the disrupted reachability.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: February 16, 2021
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Suresh Vobbilisetty, Phanidhar Koganti
  • Patent number: 10915156
    Abstract: Methods, systems, and computer program products are provided for supervised power management between a primary platform and a secondary platform. Communication between a primary platform and a secondary platform is established. An application running on the secondary platform is captured. Input features and output measures are collected to build a training set for the application, wherein the input features are collected through direct measurement and the output measures reflect characteristics of the application. Based on the training set, power consumption of the secondary platform with an expected performance level is predicted for a new application running on the secondary platform. Accordingly, an optimal power management policy is derived that minimizes the total power consumption of the primary and secondary platforms.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: February 9, 2021
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventor: Hwisung Jung
  • Patent number: 10917359
    Abstract: A vehicular communication device and method for communicating with a remote server. In various embodiments, the vehicular communication device receives a plurality of device packets from a vehicle device(s) via a vehicular communication network, including device packets having a first priority and device packets having a second priority. Processing circuitry of the vehicular communication device determines the respective priorities of the received device packets based upon the contents of the packets, and queues at least some of the received device packets (and/or informational packets derived therefrom) in accordance with the respective priorities. The queued packets are output to a remote server for processing. The vehicular communication device receives responsive content from the remote server, which may include safety content, a servicing notice and/or targeted commercial content.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: February 9, 2021
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Nariman Yousefi, Yongbum Kim, John Walley, Sherman (Xuemin) Chen, Wael W. Diab, Nicholas Ilyadis