Abstract: The present disclosure describes a system that can include an antenna; a receive (Rx) path coupled to the antenna; and a transmit (Tx) path comprising a balun; and a radio frequency (RF) attenuator comprising a first port and a second port, the balun coupled to the first port, the antenna coupled to the second port. The RF attenuator can include a first switch coupled between the first port and the second port; a second switch and a first attenuator coupled to each other in series between the first port and the second port, the first attenuator having a first attenuator value; and a third switch and a second attenuator coupled to each other in series between the first port and the second port, the second attenuator having a second attenuator value greater than the first attenuator value of the first attenuator.

Abstract: An integrated circuit for measuring current while receiving wireless power is described. The integrated circuit measures a current across a resistor by an amplifier. A gain of the amplifier is based on a pair of matched upstairs resistors and a pair of matched downstairs resistors. The pair of matched upstairs resistors may include an offset in resistance. The integrated circuit includes a switch matrix with switches coupled between the integrated resistor and the pair of matched upstairs resistors. The offset for the pair of matched upstairs resistors may be measured by selectively controlling the switches.

Abstract: Packets in a data communications network are encapsulated by an encapsulation module on a sending computer and decapsulated on the receiver computer, the transmission of data packets being controlled by credit sent by the receiving computer to avoid causing congestion. The encapsulation module varies fields in the packets that are used by switches to determine the path to the destination, so as to distribute the load of a transfer across a plurality of paths to the receiving computer. The sending and receiving computers use per path packet delivery, loss, latency and packet trimming information to detect abnormal network behavior and submit alerts and summary statistics to a monitoring station. The monitoring station uses this information to detect network bottlenecks and other faults and to localize them to specific switches or links.

Abstract: A semiconductor product being convertible or converted from a customizable configuration into a selectable or selected one of a plurality of different customized configurations, wherein the semiconductor product comprises a customizing unit configured for customizing the semiconductor product into one of the customized configurations selected by a received customizing data structure specifying a selected application of the semiconductor product, and a plurality of functional blocks each configured for providing an assigned functionality and all being deactivated when the semiconductor product is not in one of the customized configurations, wherein the customizing unit is configured for activating only a subgroup of the functional blocks based on the received customizing data structure.

Abstract: In some aspects, the disclosure is directed to methods and systems for providing a hybrid low power, high bandwidth media transport protocol between media sinks and media sources by splitting control and synchronization commands to a low power communication interface, and media data to a high bandwidth unidirectional communication interface. Media sinks need not transmit via the high bandwidth unidirectional communication interface, reducing power consumption, which may be particularly beneficial for small devices with limited battery capacity such as wireless earbuds.

Abstract: Described herein are systems, methods, and products utilizing a cache coherent switch on chip. The cache coherent switch on chip may utilize Compute Express Link (CXL) interconnect open standard and allow for multi-host access and the sharing of resources. The cache coherent switch on chip provides for resource sharing between components while independent of a system processor, removing the system processor as a bottleneck. Cache coherent switch on chip may further allow for cache coherency between various different components. Thus, for example, memories, accelerators, and/or other components within the disclose systems may each maintain caches, and the systems and techniques described herein allow for cache coherency between the different components of the system with minimal latency.

Abstract: A switch includes memory including a flow table. The flow table includes a flow key database and a flow policy database for flows in a network associated with the switch. The switch includes a security processor including an exact match engine. The exact match engine manages the flow table in the memory. The exact match engine includes a learn cache configured to store key entries for storage in the flow key database.

Abstract: A circuit includes first and second power devices that include first and second field effect transistors (FET). A first channel is located between a first drain and a first source of first FET and a second channel is located between a second drain and a second source of second FET. First and second drains are coupled to first common junction and first and second sources are coupled to second common junction. The first common junction is configured to receive a current. A switch controller is coupled to a first gate of the first FET and to a second gate of the second FET to apply a bias voltage to the first and second gates one by one and in turn. An analog to digital converter coupled to first common junction and second common junction and configured to alternately digitize a voltage of the first channel or the second channel.

Abstract: The present application relates generally to silicon photomultiplier (SiPM) detector arrays. In one aspect, there is a system including an array of cells each including a single-photon avalanche diode (SPAD) reverse-biased above a breakdown voltage of the SPAD. Each cell may further include trigger logic connected to the SPAD, and configured to output a trigger signal indicating whether the SPAD is in breakdown. Each cell may still further include a conditional recharge circuit configured to recharge the SPAD conditional upon both (i) the recharge circuit applying the recharge signal to the cell and (ii) the trigger signal output by the trigger logic of the cell indicating the SPAD of the cell is in breakdown.

Abstract: An apparatus includes an ingress data buffer, an ingress processor, an egress processor, and a recirculation data buffer. The apparatus is configured to provide unified packet recirculation via the recirculation data buffer and a single recirculation port on the ingress data buffer. The apparatus can be a switch, router or other network device.

Abstract: Disclosed herein are related to systems and methods for a multiple-input multiple-output (MIMO) communication. In one aspect, during a first time period, a master access point transmits, to a slave access point, information for a joint transmission by the master access point and the slave access point. In one aspect, the slave access point estimates synchronization information for the joint transmission, according to the information for the joint transmission. In one aspect, during a second time period after the first time period, the master access point transmits a portion of a null data packet to a station device. In one aspect, during the second time period, the slave access point transmits the portion of the null data packet to the station device, based on the synchronization information for the joint transmission. In one aspect, the station device determines steering information for the MIMO communication, according to the null data packet.

Abstract: A system for controlling jitter includes a first phase interpolator, a second phase interpolator, a first circuit configured to receive a first signal provided to the first phase interpolator, a second circuit configured to receive a second signal provided to the second phase interpolator, and a third circuit configured to provide a phase control signal in response to the first signal and the second signal. The first signal represents a first phase adjustment, and the second signal represents a second phase adjustment.

Abstract: A system for multimedia content recognition includes a cloud server and a media client including a silicon-on-chip (SoC) device to communicate with the cloud server via a network. The SoC device includes a local area network (LAN) interface to receive media content from a media source and a media monitor to analyze the received media content and to generate signature information for transmission to the cloud server or for a local analysis. The SoC device further includes an inference engine to locally analyze the signature information to detect an unauthorized access.

Abstract: A vehicle control module includes a vehicle device and a vehicle network interface. The vehicle device is operable to perform a vehicle function. The vehicle network interface facilitates communication regarding the vehicle function between the vehicle device and a vehicle network fabric in accordance with a global vehicle network communication protocol.

Abstract: An EM shielding structure for a semiconductor package is embedded in a through hole of a core layer of the semiconductor package. The EM shielding structure may include multiple vias formed by a copper plating operation. Additionally, a metal way surrounds the EM shielding structures and prevents, along with a dielectric material, unwanted EM radiation (passing through the vias) from emanating throughout the semiconductor package. The EM shielding structure can also take the form of an insert that is adhered to the core layer at a through hole of the core layer.

Abstract: A wireless communication device (alternatively, device, WDEV, etc.) includes at least one processing circuitry configured to support communications with other WDEV(s) and to generate and process signals for such communications. In one example, the circuitry is configured to generate a null data packet (NDP), transmit at least a portion of the NDP to another wireless communication device via fewer than all of a plurality of sub-channels of a communication channel, and receive feedback from the another wireless communication device that is based on the another wireless communication processing the at least the portion of the NDP that is received via the fewer than all of the plurality of sub-channels of the communication channel. In one example, the generated NDP includes at least one signal field (SIG) field therein that includes information to specify a preamble puncturing option or the information is transmitted in a previous packet.

Abstract: An apparatus includes an analog to digital converter configured to receive one or more first frames of a first component carrier signal having a first uplink-downlink subframe pattern, and receive one or more additional frames of at least one additional component carrier signal, the one more or more additional frames including one or more second frames of a second component carrier signal, the at least one additional component carrier signal including the second component carrier signal. The apparatus may further include control logic configured to activate timing skew calibration of at least one of the first or second component carrier signals based, at least in part, on an operating mode of the second component carrier signal and respective symbols of the first component carrier signal and second component carrier signal.

Abstract: In an example architecture flexible arithmetic coding system, coding circuitry of a device may receive video data that is to be coded (e.g., to be encoded or decoded) by arithmetic coding. The coding circuitry may compute at least one of a least probable symbol (LPS) range or a most probable symbol (MPS) range based on a multiplication operation. The coding circuitry may perform arithmetic coding on the video data using the at least one of the LPS range or the MPS range. Arithmetic coding may be binary arithmetic coding. The computation of the LPS range or the MPS range using the multiplication operation may reduce computational cost.

Abstract: A PCIe retimer includes read-only vendor registers with low latency mode entry and exit values. In-band low latency switching logic monitors the output of an elastic buffer for read commands of the vendor registers and, when such read commands are received, reads the corresponding address and switches a multiplexer between a link training data path and a low latency data path based on the return value of the read operation. Read commands, and therefore control of data path switching, is handled entirely in-band. Return values of the read operations indicate success or failure of mode switching to the root complex.

Abstract: In some aspects, the disclosure is directed a module for improving mechanical, electrical, or thermal performance. In some embodiments, the module includes a bottom surface, a side surface, a first solder bump disposed on the bottom surface, and a second solder bump disposed on the bottom surface. In some embodiments, the bottom surface extends in a first lateral direction and a second lateral direction perpendicular to the first lateral direction. In some embodiments, the side surface extends in a vertical direction perpendicular to the first lateral direction and the second lateral direction. In some embodiments, the second solder bump is adjacent to the side surface. In some embodiments, the first solder bump has a first length in the first lateral direction. In some embodiments, the second solder bump has a second length in the first lateral direction. In some embodiments, the first length is greater than the second length.