Abstract: A transmitter includes a first digital-to-analog converter (DAC) circuit consisting of a first set of unary cells to mix a first set of digital input data with a first clock signal. A second DAC circuit includes a second set of unary cells to mix a second set of digital input data with a second clock signal. A third circuit provides signals to the first DAC circuit and the second DAC circuit to implement an assignment scheme to assign either an in-phase (I) component or a quadrature (Q) component to the first set of unary cells and the second set of unary cells. Based on the assignment scheme, the first set of digital input data include I-data and Q-data, and the second set of digital input data include I-data and Q-data.

Abstract: Described herein are systems and methods related to a converter including a first input, a second input, and a number of digital to analog converter (DAC) cells. A DAC cell includes a first circuit, a first leg associated with a first output of the DAC cell, and a second leg associated with a second output of the DAC cell. The first circuit is configured to provide a return to zero operation. The DAC cell is configured to provide a data magnitude at a polarity on at least one of the first leg or the second leg during at least a portion of the clock cycle. The data magnitude and the polarity being provided in accordance with a first signal at the first input and a second signal at the second input.

Abstract: Spatial reuse is provided. A device can identify first symbols orthogonal to second symbols, responsive to a receipt of an indication, from a second device, of a transmission of a second message including the second symbols. The device can transmit a first message including the first symbols, simultaneously with the transmission of the second message.

Abstract: Mode hop detection is provided. A device includes circuitry to receive, from a reader element an indication of one or more properties of a magnetic medium detected by the reader element. The device includes circuitry to determine an envelope of the signal. The device includes circuitry to adjust, responsive to the envelope, a current provided to a laser configured to heat the magnetic medium.

Abstract: One way to stop electromagnetic fields from leaking outside of a module is an electric wall. Embodiments of the present disclosure are directed to emulating an electric wall with through vias. The through vias may be arranged around cavities in the printed circuit board. The density of the through vias may be selected based on an expected wavelength of the electromagnetic fields. The printed circuit board may then self-isolate components within the cavities from the electromagnetic fields.

Abstract: A system may include circuitry configured to couple a first end of a first resistor to a first input terminal of a line driver and couple a first end of a second resistor to a second input terminal of the line driver. The circuitry may be configured to receive, at a second end of the first resistor, a first signal. The circuitry may be configured to receive, at a second end of the second resistor, a second signal. The circuitry may be configured to set at least one of the first resistor or the second resistor to cause the line driver to output a predetermined range of output voltages, based at least on a voltage sensed from at least one of the first signal or the second signal.

Abstract: A circuit including a frequency divider configured to receive a plurality of first frequency input clock signals and provide a plurality of second frequency output clock signals, wherein the plurality of second frequency output clock signals are lower in frequency than the plurality of first frequency input clock signals, a phase detector configured to determine a difference between the plurality of second frequency output clock signals, a low pass filter configured to measure a clock signal spacing error associated with the plurality of second frequency output clock signals based on the difference between the plurality of second frequency output clock signals and to generate one or more control signals in response to the clock signal spacing error, and a control unit configured to generate one or more corrected first frequency input clock signals based on the one or more control signals.

Abstract: Systems and methods relate a device for monitoring or tracking clock frequency. The device can include a first circuit configured to receive a reference clock signal and provide a first signal in response to a first number of cycles of the reference clock signal, and a second circuit configured to receive a sample clock signal and provide a second signal in response to the first signal. The second signal is indicative of a second number of cycles of the sample clock signal occurring during the first number of cycles of the reference clock signal. The device can also include a third circuit configured to determine a ratio of a first frequency of the reference clock signal to a second frequency of the sample signal using the second signal.

Abstract: Systems and methods use a protocol for handoff operations. A first device using the protocol includes a circuit configured to provide at least one frame across a connection to a second device in response to a pending failure. The frame includes data indicating at least one target access point for the second device.

Abstract: Systems and methods for synchronizing multiple of output clocks. The system includes: a plurality of frequency dividers configured to receive a plurality of input clock signals and produce a plurality of output clock signals, wherein each of the plurality of output clock signals are lower in frequency than a corresponding input clock signal; and a circuit. The circuit is configured to: compare a first output clock signal of the plurality of output clock signals to a second output clock signal of the plurality of output clock signals to determine whether the first output clock signal is synchronized with the second output clock signal, generate a slip signal in response to determining that the first output clock signal is not synchronized with the second output clock signal, and apply the slip signal to the second output clock signal to synchronize the second output clock signal with the first output clock signal.

Abstract: Systems and methods use a protocol for disassociation/deauthentication. Some embodiments relate to a first device including a circuit configured to provide at least one frame across a connection to a second device during a disassociation operation or deauthentication operation. The frame can include data indicating at least one target access point for the second device. The frame can be provided according to an 802.11 protocol and the connection can be established by using an association or authentication operation.

Abstract: A system may include circuitry configured to couple a first end of a first resistor to a first input terminal of a line driver, and couple a first end of a second resistor to a second input terminal of the line driver. The circuitry may be configured to receive, at a second end of the first resistor, a first signal. The circuitry may be configured to receive, at a second end of the second resistor, a second signal. The circuitry may be configured to set resistance of at least one of the first resistor or the second resistor such that the line driver outputs a predetermined range of output voltages based at least on a voltage sensed from at least one of the first signal or the second signal.

Abstract: Systems and methods can advantageously provide a protocol. A device using the protocol can include circuitry device configured to provide at least one frame while a connection is being established. The frame includes data indicating that the device is capable of a data management multilink (DMML) operation. In some examples, the frame is provided according to an 802.11 protocol.

Abstract: A device may include one or more ring oscillators and circuitry. The one or more ring oscillators may include a plurality of rings. The circuitry may be configured to receive a selection of a number of coupled rings and a number of phases. The circuitry may be configured to configure the one or more ring oscillators to operate at least based on the number of coupled rings. The circuitry may be configured to cause the configured one or more ring oscillators to receive an input signal and output a plurality of signals having respective phases corresponding to the number of phases. The circuitry may be configured to convert the plurality of signals to one or more digital signals.

Abstract: Disclosed herein are implementations of a hybrid network for use in a full duplex communication system. In one aspect, the hybrid network includes a first circuit coupled between an output of a communication channel and a shared output of a transmitter and the communication channel, a second circuit coupled between a first output of the transmitter and the shared output, a third circuit coupled between the shared output and an input of an amplifier, a fourth circuit coupled between the input of the amplifier and a second output of the transmitter, and a fifth circuit coupled between an output of the amplifier and the input of the amplifier. In some embodiments, the output of the amplifier is coupled to an input of a receiver.

Abstract: An apparatus for detecting optical signals includes a photodetector. The photodetector is reverse-biased by a first voltage and a second voltage is added to the first voltage to provide an offset equal to the second voltage for the photodetector. A first circuit is coupled to the first circuit to provide the second voltage for the photodetector and a second circuit is coupled to the first circuit to provide the first voltage to the photodetector to reverse-bias the photodetector. The second circuit provides an output voltage proportional to a current of the photodetector at an output of the second circuit.

Abstract: Described herein are a device and a method for performing a network analysis. In one aspect, the device includes a feature extraction circuit, an input processing circuit, and a reconfigurable neural network circuit. In one aspect, the feature extraction circuit receives a raw packet stream, and obtains temporal statistics of a flow, according to a first packet attribute or a first flow attribute of the raw packet stream. In one aspect, the feature extraction circuit generates a feature data including one or more statistical features based on the temporal statistics of the flow. In one aspect, the input processing circuit scales the feature data to generate an adjusted feature data. In one aspect, the reconfigurable neural network circuit performs computations corresponding to a neural network on the adjusted feature data to determine a predicted network characteristic.

Abstract: A system includes a first circuit configured to provide a digitally pre-distorted input signal, a digital-to-analog converter including a number of unit elements, a digital input, and a digital output. Each unit element is configured to receive a reference voltage and to be controllable by a control signal provided in response to the digitally pre-distorted input signal. The digital-to-analog converter provides an analog output. The first circuit is configured to reduce distortion due to signal dependent changes to the reference voltage. The signal dependent changes can be due at least in part to current through the supply network that supplies the reference voltage. The digital to analog converter can be a voltage mode converter.

Abstract: Described herein are related to a calibration circuit for a digital to analog converter (DAC) including a plurality of DAC cells. The calibration circuit including a chopper circuit configured to receive a first signal from a first DAC cell of the plurality of DAC cells and receive a second signal from a second DAC cell of the plurality of DAC cells. The calibration circuit including a comparator circuit configured to receive the first signal and the second signal from the chopper circuit, provide a third signal indicating at least one of the first signal or the second signal. The calibration circuit also including a second circuit configured to offset a first voltage associated with the comparator circuit and configured to offset a second voltage associated with the chopper circuit.

Abstract: A device and substrate are disclosed. An illustrative device includes a substrate having a first surface and an opposing second surface, a solder material receiving curved surface exposed at the second surface of the substrate, a solder resist material that at least partially covers the solder material receiving curved surface such that a middle portion of the solder receiving curved surface is exposed and such that an edge portion of the solder material receiving curved surface is covered by the solder resist material and forms an undercut, and a solder material disposed within the solder material receiving curved surface and within the undercut.