Abstract: A headphone detector including a headphone and a processor. The headphone has a microphone and a speaker, and the microphone is configured to generate an audio signal based on an output of the speaker. The processor is configured to receive the audio signal, determine a characteristic of the audio signal, and assess whether the headphone is on ear or off ear based on a comparison of the characteristic to a threshold. In another aspect, an off-ear detection (OED) system includes a headphone and an OED processor. The headphone has a speaker, a feedforward microphone, and a feedback microphone. The OED processor is configured to determine whether the headphone is off ear or on ear, based at least in part on a headphone audio signal, a feedforward microphone signal, and a feedback microphone signal.

Abstract: A start-up circuit for a bandgap reference voltage generator circuit, including a first native transistor with a drain connected to a supply voltage of the bandgap reference voltage generator circuit and a source connected to a gate of the first native transistor; a low voltage transistor with a source connected to ground, a drain connected to the source of the first native transistor, and a gate connected to a resistor; a second native transistor with a source connected to the resistor, a gate connected to the source of the first native transistor; a high voltage transistor with a drain connected to a drain of the second native transistor and a source connected to the supply voltage; and a transistor with a gate connected to the gate of the first high voltage transistor and a drain which provides a start-up current for the bandgap reference voltage generator circuit.

Abstract: An audio system having low latency includes a digital audio processor as well as sensor inputs coupled to the processor. The sensor inputs may be microphone inputs. The audio processor operates at the same frequency as the sensor inputs, which is typically much higher than an audio signal provided to the audio processor. In some aspects the audio processor operates as a noise cancellation processor and does not include an audio input.

Abstract: A method can include a digital oversampler oversampling an input data stream, a rate generator selecting a frequency that is not less than an expected frequency of the input data stream, a rate generator clock of the rate generator outputting a clock signal that has the selected frequency, determining whether a sample receiver has received at least one sample of the input data stream from the digital oversampler, and, responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler, incrementing a sample counter by each received sample. The method can also include a sample rate converter accumulating samples from the sample receiver at the rate of a “toothless” clock signal, determining whether an output of the sample counter is greater than zero, and, responsive to a determination that the output of the sample counter is greater than zero, an AND gate passing the “toothless” clock signal to the sample rate converter.

Abstract: A circuit can include a voltage comparator Vd having a first input, a second input, and an output; a first plurality of capacitors Cp[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the first input of the voltage comparator Vd, wherein each top plate is also switchably electrically coupled with a common mode voltage Vcm, and wherein each bottom plate is switchably electrically coupled between a first input voltage Vinp, a reference voltage Vref, the common mode voltage Vcm, and ground; a second plurality of capacitors Cn[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the second input of the voltage comparator Vd, wherein each top plate is also switchably electrically coupled with the common mode voltage Vcm, and wherein each bottom plate is switchably electrically coupled between a second input voltage Vinn, the reference voltage Vref, the common mode voltage Vcm, and ground; and a successive appro

Abstract: Embodiments of the invention may be used to implement a rate converter that includes: 6 channels in forward (audio) path, each channel having a 24-bit signal path per channel, an End-to-end SNR of 110 dB, all within the 20 Hz to 20 KHz bandwidth. Embodiment may also be used to implement a rate converter having: 2 channels in a reverse path, such as for voice signals, 16-bit signal path per channel, an End-to-end SNR of 93 dB, all within 20 Hz to 20 KHz bandwidth. The rate converter may include sample rates such as 8, 11.025, 12, 16, 22.05, 24, 32 44.1, 48, and 96 KHz. Further, rate converters according to embodiments may include a gated clock in low-power mode to conserve power.

Abstract: A programmable Active Noise Compensation (ANC) system for an audio input includes a parameter store structured to store a number of various filter parameters. A mode of operation is selected that represents the type of environment the ANC system is operating in—feed-forward, feed-back, or combined feed-forward and feedback. Different filter parameters are retrieved from the parameter store based on the selected mode and desired operation. Audio inputs are sampled at a relatively high sample rate that matches inputs from a feed-forward and feedback microphone that may be present in the system. Parameters and instructions may be changed in the system responsive to changing conditions of the compensation system.

Abstract: A method of calibrating an earphone may include: securing an ANC earphone to a calibration fixture, the calibration fixture including an ear model configured to support the ANC earphone, the ear model having an ear canal configured to anatomically resemble a human ear canal and a concha configured to anatomically resemble a human ear concha, the ear canal extending from the concha to an inner end of the ear canal; generating, with the ANC earphone, an audio signal based on a reference tone; determining a characteristic of the audio signal; comparing the characteristic of the audio signal to a previously determined reference characteristic; and adjusting a gain value of the ANC earphone based on the comparing. Additional methods and apparatus are also disclosed.

Abstract: An acoustic layer is added to a keyboard-type device including: enclosing walls, optionally—one or more microphones, a signal processing device, at least one audio transducer, and an acoustic waveguide. The acoustic layer adjoins one or more internal areas of a keyboard-type device. The signal processing device receives an internal signal from an electronic device either through wires or wirelessly. The signal processing device provides a directive sound enhancement of the audio input signals based on room acoustics, such as reverberation, echo, noise, delay, frequency response, and/or speaker-positional information that is determined by the signal processing device. The audio transducer device generates an audible audio output in response to an audio signal output from the signal processing device. The acoustic waveguide receives the audible audio output and generates an enhanced bass audio output from the acoustic waveguide.

Abstract: A method for forming a complete ring network of a plurality of Bluetooth® speakers, the method including populating a configurable speaker register of each of the plurality of Bluetooth® speakers with an address of an upstream Bluetooth® speaker that is in the plurality of Bluetooth® speakers, populating the configurable speaker register of each of the plurality of Bluetooth® speakers with an address of a downstream Bluetooth® speaker that is in the plurality of Bluetooth® speakers, and coupling an audio source to one Bluetooth® speaker of the plurality of Bluetooth® speakers.

Abstract: A low power, digital audio interface includes support for variable length coding depending on content of the audio data sent from the interface. A particularized coding system is implemented that uses techniques of silence detection, dynamic scaling, and periodic encoding to reduce sent data to a minimum. Other techniques include variable packet scaling based on an audio sample rate. Differential signaling techniques are also used. The digital audio interface may be used in a headphone interface to drive digital headphones. A detector in the interface may detect whether digital or analog headphones are coupled to a headphone jack and drive the headphone jack accordingly.

Abstract: An acoustic layer is added to a laptop-type personal computing device, comprising: enclosing walls, optionally—one or more microphones, a signal processing device, at least one audio transducer, and an acoustic waveguide. The acoustic layer adjoins one or more internal areas of a laptop-type device. The signal processing device receives an internal signal from a laptop-type device. The signal processing device provides a directive sound enhancement of the audio input signals based on room acoustics, such as reverberation, echo, noise, delay, frequency response, and/or speaker-positional information that is determined by the signal processing device. The audio transducer device generates an audible audio output in response to an audio signal output from the signal processing device. The acoustic waveguide receives the audible audio output and generates an enhanced bass audio output from the acoustic waveguide.

Abstract: A tabletop speaker system includes an amplifier, proximity and acceleration detectors, and a processor. The processor is operatively coupled to receive signals from the proximity and accelerometer detectors, and in response to the proximity and acceleration signals, activate various functions local to the tabletop speaker system to operate and control various behaviors or features of the tabletop speaker system. In this way, the tabletop speaker system can respond to user gestures for a very natural control interface.

Abstract: Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.

Abstract: A system and a technique for recovering data from an input data stream without synchronization of an input sampling circuit to the input data stream determines a count of incoming samples (or frames) without generating a signal that is frequency-locked to the input data stream. A first clock is generated comprising a frequency that is greater than or equal to an expected frequency of the input data stream. A sample count is incremented in response to a sample received in the input data stream, and is decremented in response to a second clock signal. The second clock is generated from the first clock signal by passing the first clock signal if the sample count of the sample counter does not equal a predetermined sample count value and by blocking the first clock signal if the sample count equals the predetermined sample count value.

Abstract: A headphone detector including a headphone and a processor. The headphone has a microphone and a speaker, and the microphone is configured to generate an audio signal based on an output of the speaker. The processor is configured to receive the audio signal, determine a characteristic of the audio signal, and assess whether the headphone is on ear or off ear based on a comparison of the characteristic to a threshold. In another aspect, an off-ear detection (OED) system includes a headphone and an OED processor. The headphone has a speaker, a feedforward microphone, and a feedback microphone. The OED processor is configured to determine whether the headphone is off ear or on ear, based at least in part on a headphone audio signal, a feedforward microphone signal, and a feedback microphone signal.

Abstract: A method for forming a complete ring network of a plurality of Bluetooth® speakers, the method including populating a configurable speaker register of each of the plurality of Bluetooth® speakers with an address of an upstream Bluetooth® speaker that is in the plurality of Bluetooth® speakers, populating the configurable speaker register of each of the plurality of Bluetooth® speakers with an address of a downstream Bluetooth® speaker that is in the plurality of Bluetooth® speakers, and coupling an audio source to one Bluetooth® speaker of the plurality of Bluetooth® speakers.

Abstract: A circuit can include a voltage comparator Vd having a first input, a second input, and an output; a first plurality of capacitors Cp[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the first input of the voltage comparator Vd, wherein each top plate is also switchably electrically coupled with a common mode voltage Vcm, and wherein each bottom plate is switchably electrically coupled between a first input voltage Vinp, a reference voltage Vref, the common mode voltage Vcm, and ground; a second plurality of capacitors Cn[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the second input of the voltage comparator Vd, wherein each top plate is also switchably electrically coupled with the common mode voltage Vcm, and wherein each bottom plate is switchably electrically coupled between a second input voltage Vinn, the reference voltage Vref, the common mode voltage Vcm, and ground; and a successive appro

Abstract: A new compensation system for an audio input reduces noise by matching feedback ratios in the positive and negative paths. A variable resistance network allows for fine control of resistance trimming in one of the signal paths, which allows for compensation between tolerance of resistors that are external to an integrated circuit and those that are internal to the integrated circuit.

Abstract: A current-mode, digital-to-analog converter (DAC) configured to convert a digital word input having j bits to an analog signal. The DAC has 2j current sources, an output node, a current divider, a first switch, and a second switch. Each of the 2j current sources is configured to produce a current having a value I0. The current divider has a programmable divide ratio, d, where 1/d is between 0 and 1. The first switch is configured to selectively couple 2j?1 of the 2j current sources to the output node. One of the 2j current sources is not coupled to the output node. The second switch is configured to selectively couple each of the 2j current sources to the current divider. This architecture ensures that the fundamental transform of input code to output current always has a slope that does not change from positive to negative or from negative to positive.