Abstract: Embodiments of the invention may be used to implement a rate converter that includes: 6 channels in forward (audio) path, each channel having a 24-bit signal path per channel, an End-to-end SNR of 110 dB, all within the 20 Hz to 20 KHz bandwidth. Embodiment may also be used to implement a rate converter having: 2 channels in a reverse path, such as for voice signals, 16-bit signal path per channel, an End-to-end SNR of 93 dB, all within 20 Hz to 20 KHz bandwidth. The rate converter may include sample rates such as 8, 11.025, 12, 16, 22.05, 24, 32 44.1, 48, and 96 KHz. Further, rate converters according to embodiments may include a gated clock in low-power mode to conserve power.

Abstract: A memory address space for each of a plurality of physical memories in a microprocessor-based system is allocated prior to knowing the desired logical size of at least one of the physical memories. At least two of the allocated memory address spaces overlap at least a portion of each other. After the system is fabricated, a pointer value set that corresponds to an address boundary between at least two physical memories of the fabricated system is set during boot time and/or during run time when the size of the physical memories are known. The technique provides a faster time-to-market for microprocessor-based systems by allowing, for example, Application Specific Integrated Circuits (ASICs) comprising microprocessor systems on-chip be manufactured prior to the final firmware and software being fully developed. Additionally, the subject matter disclosed herein permits changes in memory-space allocation for finalized ASIC designs.

Abstract: A soundskin for a pad-type device comprises a housing, at least one microphone, a signal processing device, at least one audio transducer, and an acoustic waveguide. The housing receives a pad-type device. The signal processing device receives a signal from a pad-type device when the pad-type device is received by the housing. The signal processing device provides a directive sound enhancement of the audio input signals based on room acoustics, such as reverberation, echo, noise, delay, frequency response, and/or speaker-positional information that is determined by the signal processing device. The audio transducer device generates an audible audio output in response to an audio signal output from the signal processing device. The acoustic waveguide receives the audible audio output and generates an enhanced bass audio output from the acoustic waveguide.

Abstract: A tabletop speaker system includes an amplifier, proximity and acceleration detectors, and a processor. The processor is operatively coupled to receive signals from the proximity and accelerometer detectors, and in response to the proximity and acceleration signals, activate various functions local to the tabletop speaker system to operate and control various behaviors or features of the tabletop speaker system. In this way, the tabletop speaker system can respond to user gestures for a very natural control interface.

Abstract: A programmable Active Noise Compensation (ANC) system for an audio input includes a parameter store structured to store a number of various filter parameters. A mode of operation is selected that represents the type of environment the ANC system is operating in—feed-forward, feed-back, or combined feed-forward and feedback. Different filter parameters are retrieved from the parameter store based on the selected mode and desired operation. Audio inputs are sampled at a relatively high sample rate that matches inputs from a feed-forward and feedback microphone that may be present in the system. Parameters and instructions may be changed in the system responsive to changing conditions of the compensation system.

Abstract: A device and method are disclosed for modulating a power converter based on an audio signal to directly drive a speaker with a differential audio output signal. A first modulation signal and a second modulation signal are generated based on an input audio signal so that the first and second modulation signals are complementary signals to each other. In one embodiment, a feedback signal, such as an acoustic feedback signal from the speaker, is also used to generate the first and second modulation signals. A power supply voltage is modulated with the first modulation signal to generate a first voltage signal. The power supply voltage is also modulated with the second modulation signal to generate a second voltage signal. The first and second voltage signals form a differential audio signal that is used to drive the speaker. Alternatively, the power converter can drive a speaker with a single-ended output signal.

Abstract: A system and a technique for recovering data from an input data stream without synchronization of an input sampling circuit to the input data stream determines a count of incoming samples (or frames) without generating a signal that is frequency-locked to the input data stream. A first clock is generated comprising a frequency that is greater than or equal to an expected frequency of the input data stream. A sample count is incremented in response to a sample received in the input data stream, and is decremented in response to a second clock signal. The second clock is generated the first clock signal by passing the first clock signal if the sample count of the sample counter does not equal a predetermined sample count value and by blocking the first clock signal if the sample count equals the predetermined sample count value.

Abstract: A system and a technique for recovering data from an input data stream without synchronization of an input sampling circuit to the input data stream determines a count of incoming samples (or frames) without generating a signal that is frequency-locked to the input data stream. A first clock is generated comprising a frequency that is greater than or equal to an expected frequency of the input data stream. A sample count is incremented in response to a sample received in the input data stream, and is decremented in response to a second clock signal. The second clock is generated the first clock signal by passing the first clock signal if the sample count of the sample counter does not equal a predetermined sample count value and by blocking the first clock signal if the sample count equals the predetermined sample count value.

Abstract: An acoustic layer is added to a laptop-type personal computing device, comprising: enclosing walls, optionally—one or more microphones, a signal processing device, at least one audio transducer, and an acoustic waveguide. The acoustic layer adjoins one or more internal areas of a laptop-type device. The signal processing device receives an internal signal from a laptop-type device. The signal processing device provides a directive sound enhancement of the audio input signals based on room acoustics, such as reverberation, echo, noise, delay, frequency response, and/or speaker-positional information that is determined by the signal processing device. The audio transducer device generates an audible audio output in response to an audio signal output from the signal processing device. The acoustic waveguide receives the audible audio output and generates an enhanced bass audio output from the acoustic waveguide.

Abstract: A memory address space for each of a plurality of physical memories in a microprocessor-based system is allocated prior to knowing the desired logical size of at least one of the physical memories. At least two of the allocated memory address spaces overlap at least a portion of each other. After the system is fabricated, a pointer value set that corresponds to an address boundary between at least two physical memories of the fabricated system is set during boot time and/or during run time when the size of the physical memories are known. The technique provides a faster time-to-market for microprocessor-based systems by allowing, for example, Application Specific Integrated Circuits (ASICs) comprising microprocessor systems on-chip be manufactured prior to the final firmware and software being fully developed. Additionally, the subject matter disclosed herein permits changes in memory-space allocation for finalized ASIC designs.

Abstract: A system and method dynamically selects digital-to-analog (DAC) circuit elements to provide a True differential-output delta-sigma (??) DAC. The sign and magnitude of a received N-bit input code is determined. If the input code comprises a positive value, m+r circuit elements are selected from a plurality of circuit elements by a positive element selector, in which comprises a number of rotational elements, and r circuit elements are selected by a negative element selector. Each selected circuit element comprises a circuit element that was not selected for an immediately preceding received input code and has a corresponding minimum usage count value. If the input digital code comprises a negative value, m+r circuit elements are selected by the negative element selector, and r circuit elements are selected by the positive element selector. The circuit elements are capable of being configured as positive or negative circuit elements.

Abstract: A flash memory system for an A/V player, utilizing a two-level round-robin write scheme upon N flash memory planes, enabling the A/V player to be loaded with data at a data throughput essentially N times the write throughput of one of the flash memory planes. The flash chips' memory cores and data registers, and the memory system's write buffers, can be kept fully utilized during data writing.

Abstract: A circuit architecture, or topology, that provides a level shifter substantially independent of the duty cycle of an input signal includes an H-bridge arrangement of field effect transistors, a pair of capacitively coupled input terminals connected to the gates of the high-side transistors and circuitry to set the bias voltage at the gates of the high-side transistors, wherein the bias voltage generation circuitry receives at least information indicative of both the H-bridge power supply voltage and the modulation of the input signal. Various embodiments include a switchable element coupled in series with a voltage divider portion in the bias voltage generation circuitry. The ratio of on to off time of the switchable element determines the average current through the voltage divider and thus the bias voltage. To prevent excessive short-circuit current flow through the high-side transistors, the switchable elements are turned off responsive to detection of a short-circuit condition.

Abstract: A differential feedback amplifier is provided with a feedback network wherein that feedback network is adjustable so as to improve the PSRR of the amplifier. In another aspect of the present invention, a differential feedback amplifier is provided with a feedback network wherein that feedback network is adjustable so as to improve the CMRR of the amplifier. In a further aspect of the present invention, a Class D amplifier is provided with a passive differential feedback, summing with an input current at a differential virtual ground produced by an amplifier which is a sub-section of the Class D amplifier.

Abstract: Systems and methods for communicating source data between a source device and a listener device are disclosed. In an exemplary embodiment, source data is encoded by organizing at least a selected portion of source data into a data block having rows and columns. Encoded columns are formed by appending to each column error correction data derived from that column using a selected error correction code. Encoded rows are formed by appending to each row error correction data derived from that row using a selected error correct code. In an exemplary embodiment, encoded rows of source data (together with appended FEC data) and a first predetermined number of rows of FEC data are transmitted together, such that the first predetermined number of rows is less than all rows of error correction data. In an exemplary embodiment, source data is organized using interleaving.

Abstract: A circuit architecture, or topology, that provides a level shifter which is substantially independent of the duty cycle of an input signal includes an H-bridge arrangement of field effect transistors, a pair of capacitively coupled inputs terminals connected to the gates of the high-side (i.e., connected to the positive power supply) transistors and a pair of voltage dividers to set the bias voltage at the gates of the high-side transistors, wherein one side of each voltage divider is coupled to the power supply node and the other side of each voltage divider is cross-coupled to the output node of the opposite side of the H- bridge.

Abstract: A circuit architecture, or topology, that provides a level shifter which is substantially independent of the duty cycle of an input signal includes an H-bridge arrangement of field effect transistors, a pair of capacitively coupled inputs terminals connected to the gates of the high-side (i.e., connected to the positive power supply) transistors and a pair of voltage dividers to set the bias voltage at the gates of the high-side transistors, wherein one side of each voltage divider is coupled to the power supply node and the other side of each voltage divider is cross-coupled to the output node of the opposite side of the H-bridge.

Abstract: A wireless communication system includes a wireless terminal and a host device. The wireless terminal includes a transceiver and a processor. The transceiver of the wireless terminal transmits electrical audio signals output from a plurality of microphones over a wireless communication link for enhancement processing, such as noise-cancellation processing, echo-cancellation processing, and/or sidetone processing, at the host device. The wireless communication link can be an electromagnetic-based wireless communication link, a light-based wireless communication link and/or a magnetic-induction-based wireless communication link. The transceiver of the wireless terminal further receives from the wireless communication link enhancement-processed signals based on the electrical audio signals. The processor of the wireless terminal uses the enhancement-processed signals to output an enhanced audio output signal from the terminal device.

Abstract: A radio receiver channel includes an analog front end and a digital signal processing section coupled together by an analog-to-digital converter (ADC) having a delta-sigma modulator coupled to a first digital decimation filter, which is coupled to second digital decimation filter, wherein the first decimation filter includes a source of finite impulse response coefficients coupled so as to provide a plurality of coefficients. The delta-sigma modulator includes a loop filter having a plurality of serially coupled integrators, and a multi-bit quantizer coupled to the loop filter; the multi-bit quantizer including an ADC operable to produce a multi-bit digital output signal, the ADC coupled to a DAC having dual DAC feedback loops, and a dynamic element matching function.