Abstract: An interface circuit may convert an input electrical signal at an input node in a first power domain having a first ground or reference voltage into an output electrical signal at an output node in a second power domain having a second ground or reference voltage. Notably, a level-shifting circuit in the interface circuit may selectively electrically couple to the input node and the output node. Then, when there is electrical coupling, the level-shifting circuit may perform level shifting between the first power domain and the second power domain. The level shifting may involve: passing, using a first filter, frequencies in the input electrical signal below a first corner frequency; passing, using a second filter in parallel with the first filter, frequencies in the input electrical signal above a second corner frequency; and combining outputs of the first filter and the second filter as the output electrical signal.

Abstract: Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.

Abstract: An integrated circuit is described. This integrated circuit may include: a receive circuit, coupled to a segment of a LIN bus, that receives bits; a measurement circuit, coupled to the receive circuit, that measures: a rising-edge time and a falling-edge time in the bits, or a bit time and a second bit time in the bits; control logic, coupled to the measurement circuit, that compares the rising-edge time and the falling-edge time, or the bit time and the second bit time; a transmit circuit, coupled to the receive circuit, that transmits the bits on a second segment of the LIN bus; and a delay circuit, coupled to the control logic, that applies, based at least in part on the comparison, a delay to: one or more rising edges or falling edges in the bits; or one or more bit times or second bit times in the bits.

Abstract: Multiple-input multiple-output (MIMO) radar systems are equipped with channel extenders to further increase the number of receive and/or transmit antennas that can be supported by a given radar transceiver. One illustrative radar system includes: a radar transceiver to generate a transmit signal and to downconvert at least one receive signal; and a receive-side extender that couples to a set of multiple receive antennas to obtain a set of multiple input signals, that adjustably phase-shifts each of the multiple input signals to produce a set of phase-shifted signals, and that couples to the radar transceiver to provide the at least one receive signal, the at least one receive signal being a sum of the phase-shifted signals. An illustrative receive-side extender includes: multiple phase shifters each providing an adjustable phase shift to a respective input signal; a power combiner that forms a receive signal by combining outputs of the multiple phase shifters.

Abstract: An integrated circuit is described. This integrated circuit may include: an interface module with a first power domain and a second power domain. The first power domain may include a digital controller, and the second power domain may include a first analog front end (AFE) circuit. Moreover, the interface module may include up/down level shifters that communicate electrical signals that include a DC component from the first power domain to the second power domain. In some embodiments, the integrated circuit may provide a fully on-chip solution to handle level shifting between the AFE circuit and a digital controller in Universal Serial Bus (USB) 2.0 during communication of electrical signals in a full-speed mode and/or a high-speed mode.

Abstract: An integrated circuit that includes a generating circuit is described. During operation, the generating circuit may provide an edge clock having a target phase within a clock period of an input clock, where the generating circuit does not include a delay-locked loop (DLL). For example, the generating circuit may include a gated ring oscillator that provides a reference clock having a first fundamental frequency that is larger than a second fundamental frequency of the input clock. Note that the gated ring oscillator may be programmable to adjust the first fundamental frequency within a predefined range of values. Moreover, the generating circuit may include a control circuit that determines a reference count of a number of edges of the reference clock within a reference period of the reference clock.

Abstract: Disclosed active reflector apparatus and methods that inhibit self-induced oscillation. One illustrative apparatus embodiment includes an amplifier and an adjustable phase shifter. The amplifier amplifies a receive signal to generate a transmit signal, the transmit signal causing interference with the receive signal. The adjustable phase shifter modifies the phase of the transmit signal relative to that of the receive signal to inhibit oscillation. A controller may periodically test a range of settings for the adjustable phase shifter to identify undesirable phase shifts prone to self-induced oscillation, and may maintain the phase shift setting at a value that inhibits oscillation.

Abstract: An integrated circuit may include a full-scale reference generation circuit that corrects for variation in the gain or full scale of a set of interleaved analog-to-digital converters (ADCs). Notably, the full-scale reference generation circuit may provide a given full-scale or reference setting for a given interleaved ADC, where the given full-scale setting corresponds to a predefined or fixed component and a variable component (which may specify a given full-scale correction for a given full scale). For example, the full-scale reference generation circuit may include a full-scale reference generator replica circuit that outputs a fixed current corresponding to the fixed component. Furthermore, the full-scale reference generation circuit may include a full-scale reference generator circuit that outputs a first voltage corresponding to the given full-scale setting based at least in part on the fixed current and a variable current that, at least in part, specifies the given full-scale correction.

Abstract: An integrated circuit is described. This integrated circuit may include a control circuit. During operation, the control circuit may detect when an output current provided to a load exceeds a current threshold. Moreover, in response to the detection, the control circuit may reduce a loop gain associated with an amplifier in the control circuit. Note that the output current may be associated with a switched-mode power supply. For example, the reduced loop gain may transition the switched-mode power supply from a constant voltage mode to a constant current mode. In some embodiments, the output current may be associated with a power supply or a source. Notably, the reduced loop gain may transition the power supply or the source from a constant voltage mode to a constant current mode.

Abstract: A centralized occupancy detection system enables monitoring of multiple seats, or more generally, multiple stations, with a single sensor. One illustrative vehicle includes: one or more stations each configured to accommodate an occupant of the vehicle, a radar-reflective surface, and a radar transceiver configured to use the radar-reflective surface to detect an occupant of at least one of the stations. Another illustrative vehicle includes: multiple stations to each accommodate an occupant of the vehicle, and a radar transceiver configured to examine each of the multiple stations to determine whether that station has an occupant.

Abstract: An integrated circuit that includes a generating circuit is described. During operation, the generating circuit may provide an edge clock having a target phase within a clock period of an input clock, where the generating circuit does not include a delay-locked loop (DLL). For example, the generating circuit may include a gated ring oscillator that provides a reference clock having a first fundamental frequency that is larger than a second fundamental frequency of the input clock. Note that the gated ring oscillator may be programmable to adjust the first fundamental frequency within a predefined range of values. Moreover, the generating circuit may include a control circuit that determines a reference count of a number of edges of the reference clock within a reference period of the reference clock.

Abstract: An interface circuit may convert an input electrical signal at an input node in a first power domain having a first ground or reference voltage into an output electrical signal at an output node in a second power domain having a second ground or reference voltage. Notably, a level-shifting circuit in the interface circuit may selectively electrically couple to the input node and the output node. Then, when there is electrical coupling, the level-shifting circuit may perform level shifting between the first power domain and the second power domain. The level shifting may involve: passing, using a first filter, frequencies in the input electrical signal below a first corner frequency; passing, using a second filter in parallel with the first filter, frequencies in the input electrical signal above a second corner frequency; and combining outputs of the first filter and the second filter as the output electrical signal.

Abstract: An integrated circuit that controls distributed temperature sensors in a semiconductor die is described. This integrated circuit may include: memory; a controller (such as a PTAT controller) coupled to the memory; temperature sensors distributed at measurement locations in the semiconductor die (such as remote locations from the controller), where a given temperature sensor includes building blocks (or components) that are common to the temperature sensors; and routing between the controller and the building blocks over an addressable bus, where signal lines for analog signals in the addressable bus are reused when communicating between the controller and different temperature sensors.

Abstract: In an illustrative integrated circuit, a chirp generator provides a chirp signal having linearly-ramped chirp intervals, while a shift frequency generator provides a signal having a different shift frequency during each of multiple segments in each chirp interval. A modulator combines the signals to derive a segmented chirp signal having multiple linearly-ramped chirp segments in each chirp interval. The modulator may be a single sideband modulator to provide frequency up-shifted and frequency down-shifted chirp segments. The segmented chirp signal may be suppressed during resettling intervals of the original chirp signal.

Abstract: An automotive radar system includes multiple radar antennas and a radar front end chip. The front end chip includes a plurality of phase rotators coupled to a local oscillator, wherein each phase rotator of the plurality of phase rotators is coupled to multiple digital phase modulators; a plurality of switches that couple selectable ones of the multiple digital phase modulators to respective amplifiers, each amplifier coupled to a respective antenna output; and a controller which provides digital control signals to the plurality of phase rotators, the multiple digital phase modulators, and the plurality of switches to synthesize transmit signals for each of the multiple radar antennas.

Abstract: Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.

Abstract: An integrated circuit with an interface circuit is described. During operation, the interface circuit may receive signals corresponding to a header of a frame that is compatible with a serial communication protocol, where the received signals include a temporal pattern of binary bits with instances of a dominant signal level and a recessive signal level. Then, the interface circuit may compute a set of conditions based at least in part on the receive signals, where, when valid, the set of conditions identify a first dominant bit in the binary bits having the dominant signal level. Moreover, when the set of conditions are valid, the interface circuit may: determine a location of synchronization field in the header relative to the identified first dominant bit; and calculate a baud rate of the receive signals based at least in part on a subset of the binary bits in the synchronization field.

Abstract: An automotive radar system includes multiple radar antennas and a radar front end chip. The front end chip includes a plurality of phase rotators coupled to a local oscillator, wherein each phase rotator of the plurality of phase rotators is coupled to multiple digital phase modulators; a plurality of switches that couple selectable ones of the multiple digital phase modulators to respective amplifiers, each amplifier coupled to a respective antenna output; and a controller which provides digital control signals to the plurality of phase rotators, the multiple digital phase modulators, and the plurality of switches to synthesize transmit signals for each of the multiple radar antennas.

Abstract: An integrated circuit that controls distributed temperature sensors in a semiconductor die is described. This integrated circuit may include: memory; a controller (such as a PTAT controller) coupled to the memory; temperature sensors distributed at measurement locations in the semiconductor die (such as remote locations from the controller), where a given temperature sensor includes building blocks (or components) that are common to the temperature sensors; and routing between the controller and the building blocks over an addressable bus, where signal lines for analog signals in the addressable bus are reused when communicating between the controller and different temperature sensors.

Abstract: Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.