Abstract: Methods and apparatus for controlling critical races in sequential circuits so that the there are no conflicts when two or more different data signals exists on shared circuit paths. This enables the design and implementation of sequential circuits having fewer gates than conventional circuit designs of equivalent function that translates into smaller area and power consumption. The control of the critical race is accomplished by adjusting the relative delay of the individual sections of one or more loops.

Abstract: A degassed polyester varnish is applied to the transduction driver to increase surface dielectric strength (insulation resistance), driver voltage breakdown, physical protection, and heat and water resistance. A vacuum chamber application process is used to apply the polyester varnish. The disclosed coating technique is applicable to all transducer drive materials and all transducer types.

Abstract: A high brightness, high color saturation liquid crystal display permits direct sunlight viewing. The display includes one or more diffractive color separation microlenses, in one embodiment, trimodal, which serves both to spatially separate incoming white light into red, green and blue bands and to focus the bands onto a subpixel matrix. A stepped and segmented surface of at least one microlens enables that microlens to provide a plurality of diffraction patterns.

Abstract: Radiation synthesizer systems provide efficient wideband operation with an antenna, such as a loop, which is small relative to operating wavelength. Energy dissipation is substantially reduced by cycling energy back and forth between a high-Q radiator and a storage capacitance under control of a switching circuit. In addition to transmit operation using an energy source such as a battery, by reciprocity receive systems deliver received signals to an output device, such as a speaker or other audio or visual transducer device. By efficient direct processing, via controlled activation of switch devices of switch modules, incident RF signals are converted to baseband signals. Commercial type AM receivers may be provided without IF processing and detection or analog filters.

Abstract: An SEU immune logic architecture includes a dual path logic gate coupled to a dual to single path converter. A first and a second logic element within the dual path logic gate are functionally and possibly structurally equivalent, and are coupled to receive input signals spanning redundant input signal sets. A given logic structure within the first logic element may receive specified input signals within a particular input signal set, while an analogous logic structure within the second logic element may receive corresponding input signals within the counterpart input signal set. A radiation induced transient pulse that affects one input signal may affect an output signal asserted by one logic structure; however, since the transient pulse doesn't affect a corresponding input signal applied to the analogous logic structure, the dual path logic gate may output at least one correctly valued signal when a transient pulse occurs.

Abstract: A method for providing a fill pattern for integrated circuit designs is disclosed. A keepout file having keepout data is generated from a chip design layout file having chip design layout data. The keepout file includes a map of areas of an integrated circuit design where fill patterns cannot be placed. The map of areas from the keepout file is then overlaid with a fill pattern to yield a fill-pattern file. Fill patterns from the fill-pattern file is removed from locations that coincide with locations as defined by the keepout data to yield a final-fill file with crucial fill pattern data. The crucial fill pattern data from the final-fill file is overlaid on the design layout data in the chip design layout file to yield a complete design layout file. Finally, the design rule integrity and logical to physical correspondence of the complete design layout file is verified.

Abstract: Radiation synthesizer systems provide efficient wideband operation with an antenna, such as a loop, which is small relative to operating wavelength. Energy dissipation is substantially reduced by cycling energy back and forth between a high-Q radiator and a storage capacitance. Systems using multi-segment loop antennas match antenna input impedance to switching circuit parameters. Control signal feeds employ fiber-optic cables and reduce conductive paths. Multi-voltage DC supply configurations use parallel conductor portions of antenna loop segments and reduce the need for separate DC supply conductors. Spurious conductive loops are thereby reduced and lightweight, flexible antenna constructions are enabled.

Abstract: The present invention pertains to radiant energy systems and more particularly to systems exhibiting the retroreflection principle wherein the system comprises a focusing means and a surface exhibiting some degree of reflectivity positioned near the focal plane of the device, and wherein incident radiation falling within the field-of-view of said system is reflected back in a direction which is parallel to the incident radiation. The present invention has great applicability in military optical system applications for detecting the presence of an enemy employing surveillance equipment and for neutralizing this surveillance capability.

Abstract: A high density, exceptionally complex and compact ultrasound transducer array using multi-layer structures composed of active integrated circuit devices on various substrates and passive devices. Electrically conducting interconnections between substrates are implemented with micro-vias configured with conductors extending through the substrates, permitting the use of divided or different integrated circuit technologies arranged and/or isolated within different integrated circuit substrates or layers of the ultrasound transducer assembly. The various layers may be assembled with solders of respectively lower reflow temperatures, to permit testing of selected layers and circuits prior to completion.

Abstract: A bridge amplifier includes a first input node connectable to a power source having an input voltage, a second input node connectable to a control source having a control voltage, and a first and a second output node. A first amplifier module having a gain is coupled between the first and second input nodes and between the first and second output nodes, and a second amplifier module is coupled to the first input node and between the first and second output nodes. The first amplifier module compares a voltage differential between the first and second output nodes to the control voltage and provides an output voltage at the first output node necessary to maintain the voltage differential at a level substantially equal to a product of the control voltage multiplied by the gain.

Abstract: A wideband double monopole meanderline loaded antenna having a single feed a single feed is disclosed. Equalizing delay lines of the antenna can be manipulated to equalize reactance of the antenna thereby enabling proper impedance matching.

Abstract: A CMOS SRAM cell with prescribed power-on data state having first and second cross-coupled inverters each defined by serially connected complementary MOS transistors (T1/T2; T3/T4) serially connected between Vdd and circuit ground to form a first inverter with a first data node (A) between the two transistors (T1/T2) of the first inverter, and, in a similar manner, to form a second inverter with a second data node (B) between the two transistors (T3/T4) of the second inverter. The gates of transistors of each inverter are connected together and cross-coupled to the data node of the other inverter. An access transistor (T5) is connected between a bit line (BL) and the first data node (A) and another access transistor (T6) is connected between a complementary bit line (BLC) and the second data node (B) to provide data access thereto.

Abstract: A high-performance high-density CMOS SRAM cell (MC) having first and second cross-coupled inverters each defined by serially connected complementary MOS transistors (TA/TC; TB/TD) serially connected between Vdd and circuit ground to form a first inverter with a first data node (1) between the two transistors (TA/TC) of the first inverter, and, in a similar manner, to form a second inverter with a second data node (2) between the two transistors (TB/TD) of the second inverter. The gates of transistors of each inverter are connected together and cross-coupled to the data node of the other inverter. An access transistor (TE) is connected between a bit line (BL) and the first data node (1) to provide data access thereto. A diode (D) is connected between the data node of one of the inverters and the common gate connection of the other inverter to facilitate the “write one” operation.

Abstract: An integrated circuit device having a built-in thermoelectric cooling mechanism is disclosed. The integrated circuit device includes a package and a substrate. Contained within the package, the substrate has a front side and a back side. Electric circuits are fabricated on the front side of the substrate, and multiple thermoelectric cooling devices are fabricated on the back side of the same substrate. The thermoelectric cooling devices are utilized to dissipate heat generated by the electric circuits to the package.

Abstract: An under voltage lockout {overscore (RESET)} circuit is connected to the {overscore (RESET)} terminal of a EEPROM. The EEPROM is used in a system which may include a computer or processor and which may be used in space. The under voltage lockout {overscore (RESET)} circuit maybe an under voltage lockout circuit used on a LinFinity SG1526/B or a Unitrode UC1526 regulating pulse width modulator which maintain the {overscore (RESET)} voltage low at all values of power supply voltage source voltage less than a predetermined level. In one embodiment the under voltage lockout {overscore (RESET)} circuit output voltage does not have a “floating voltage” which rises to a level higher than its value when a comparator initially senses that a power supply voltage source voltage is less than the predetermined amount. This is a flat {overscore (RESET)} characteristic under voltage lockout.

Abstract: A method of forming a plurality of micro column interconnection structures on a semiconductor includes providing a semiconductor layer. A photoresist layer is formed on the semiconductor layer. A plurality of cavities are etched in the photoresist layer. The plurality of cavities extend through the photoresist layer to the semiconductor layer. Solder is deposited in the plurality of cavities, thereby forming a plurality of micro columns of solder.

Abstract: Methods for manufacturing microchips are provided. A plurality of alternating metallic wiring-layers and non-metallic layers, terminating with a metallic wiring-layer, are formed on a wafer. A plurality of vias is formed for electrically interconnecting various metallic wiring-layers. A plurality of electrically conducting pads is formed adjacent various vias. A passivation layer is formed adjacent the terminal metallic wiring-layer and the plurality of conducting pads. A portion of the passivation layer is removed to expose the plurality of conducting pads. A layer is formed adjacent the passivation layer and the plurality of exposed conducting pads for protecting the microchip against electromagnetic radiation. A portion of the protective layer is removed to expose the plurality of conducting pads. Each conducting pad is electrically isolated from the protective layer. An electrically conducting bump is formed on each conducting pad.

Abstract: A library tool suite supplements conventional design tools to increase the speed, automation and accuracy of creating physical designs for a library of cells to be used in chip designs. The tool suite may include a post operations tool, an audit tool, a custom interface, a setup file and a place and route model preparation utility which interact with the conventional tools and design data to automate and ensure integrity of the physical design process. The tool suit facilitates automatically generating libraries corresponding to an overall cell plan, generating attributes defining strength of connection between possible pin placements within a cell to facilitate routing inter-cell nets through a cell, and auditing cells for errors prior to inclusion in a manufacturing library.

Abstract: The present invention provides a broadband RF absorptive structure based on a classic Salisbury screen. Closely-spaced frequency selective surface reflective layers interact with a ground plane to reflect coherent signals at 377&OHgr; into a spacecloth front layer. The frequency response of the absorptive structure is relatively flat across an octave (i.e. a 2:1 frequency ratio) bandwidth. The overall thickness of the inventive structure is less than &lgr;/4 thickness of the interactions of the FSS layers and the ground plane.

Abstract: An integrated resistor includes a resistor body region and a resistor contact region that is aligned with the body region. Because the resistor includes an aligned body and contact, it often occupies a smaller area than prior integrated resistors having a similar resistance value. A method for forming such a resistor is also disclosed.