Abstract: A high-performance high-density CMOS SRAM cell (MC) having first and second cross-coupled inverters each defined by serially connected complementary MOS transistors (TA/TC; TB/TD) serially connected between Vdd and circuit ground to form a first inverter with a first data node (1) between the two transistors (TA/TC) of the first inverter, and, in a similar manner, to form a second inverter with a second data node (2) between the two transistors (TB/TD) of the second inverter. The gates of transistors of each inverter are connected together and cross-coupled to the data node of the other inverter. An access transistor (TE) is connected between a bit line (BL) and the first data node (1) to provide data access thereto. A diode (D) is connected between the data node of one of the inverters and the common gate connection of the other inverter to facilitate the “write one” operation.

Abstract: An integrated circuit device having a built-in thermoelectric cooling mechanism is disclosed. The integrated circuit device includes a package and a substrate. Contained within the package, the substrate has a front side and a back side. Electric circuits are fabricated on the front side of the substrate, and multiple thermoelectric cooling devices are fabricated on the back side of the same substrate. The thermoelectric cooling devices are utilized to dissipate heat generated by the electric circuits to the package.

Abstract: The method comprises positioning two components adjacent each other so as to define a space between them, bridging edges of the space with webs and filling the space with flowable material such as adhesive. A fabric is preferably arranged in the space and is impregnated by the flowable material as it is drawn into the space.

Abstract: An under voltage lockout {overscore (RESET)} circuit is connected to the {overscore (RESET)} terminal of a EEPROM. The EEPROM is used in a system which may include a computer or processor and which may be used in space. The under voltage lockout {overscore (RESET)} circuit maybe an under voltage lockout circuit used on a LinFinity SG1526/B or a Unitrode UC1526 regulating pulse width modulator which maintain the {overscore (RESET)} voltage low at all values of power supply voltage source voltage less than a predetermined level. In one embodiment the under voltage lockout {overscore (RESET)} circuit output voltage does not have a “floating voltage” which rises to a level higher than its value when a comparator initially senses that a power supply voltage source voltage is less than the predetermined amount. This is a flat {overscore (RESET)} characteristic under voltage lockout.

Abstract: A method of forming a plurality of micro column interconnection structures on a semiconductor includes providing a semiconductor layer. A photoresist layer is formed on the semiconductor layer. A plurality of cavities are etched in the photoresist layer. The plurality of cavities extend through the photoresist layer to the semiconductor layer. Solder is deposited in the plurality of cavities, thereby forming a plurality of micro columns of solder.

Abstract: Methods for manufacturing microchips are provided. A plurality of alternating metallic wiring-layers and non-metallic layers, terminating with a metallic wiring-layer, are formed on a wafer. A plurality of vias is formed for electrically interconnecting various metallic wiring-layers. A plurality of electrically conducting pads is formed adjacent various vias. A passivation layer is formed adjacent the terminal metallic wiring-layer and the plurality of conducting pads. A portion of the passivation layer is removed to expose the plurality of conducting pads. A layer is formed adjacent the passivation layer and the plurality of exposed conducting pads for protecting the microchip against electromagnetic radiation. A portion of the protective layer is removed to expose the plurality of conducting pads. Each conducting pad is electrically isolated from the protective layer. An electrically conducting bump is formed on each conducting pad.

Abstract: A mobile radar system including Electronic Support Measures (ESM) which is adapted to detect and decode Identify Friend or Foe (IFF) signals. The system includes means for decoding or decrypting received IFF signals. The system uses an Electronic Counter Measure (ECM) transmitter which is adapted to transmit IFF response and interrogation signals. The IFF signals to be transmitted can be encrypted. Integrating IFF means into the ESM and ECM components results in mass and volume savings due to shared use of the transmitting and receiving resources. As the IFF signals are transmitted using ESM antennas, they can be directed towards a particular aircraft, thereby reducing spurious transmissions.

Abstract: Includes means for monitoring the position and behavior of air traffic in the vicinity of the aircraft and generating a warning or avoidance signal for air traffic predicted to be on a collision course. The apparatus also includes means for monitoring the position and behavior of the aircraft relative to terrain in the vicinity of the aircraft flight path to generate a warning or avoidance signal for terrain features predicted to provide a collision threat. Means are provided for receiving the traffic warning signals and terrain warning signals comparing the signals and generating a combined warning or advisory signal which indicates an action for the aircraft which avoids both air traffic and terrain collisions.

Abstract: The present invention provides a broadband RF absorptive structure based on a classic Salisbury screen. Closely-spaced frequency selective surface reflective layers interact with a ground plane to reflect coherent signals at 377&OHgr; into a spacecloth front layer. The frequency response of the absorptive structure is relatively flat across an octave (i.e. a 2:1 frequency ratio) bandwidth. The overall thickness of the inventive structure is less than &lgr;/4 thickness of the interactions of the FSS layers and the ground plane.

Abstract: A library tool suite supplements conventional design tools to increase the speed, automation and accuracy of creating physical designs for a library of cells to be used in chip designs. The tool suite may include a post operations tool, an audit tool, a custom interface, a setup file and a place and route model preparation utility which interact with the conventional tools and design data to automate and ensure integrity of the physical design process. The tool suit facilitates automatically generating libraries corresponding to an overall cell plan, generating attributes defining strength of connection between possible pin placements within a cell to facilitate routing inter-cell nets through a cell, and auditing cells for errors prior to inclusion in a manufacturing library.

Abstract: An integrated resistor includes a resistor body region and a resistor contact region that is aligned with the body region. Because the resistor includes an aligned body and contact, it often occupies a smaller area than prior integrated resistors having a similar resistance value. A method for forming such a resistor is also disclosed.

Abstract: The increasing use of vehicles powered completely or in part by electric motors has created a need for measuring high currents in an inexpensive, reliable and convenient manner for digital motor control. Because the operating voltages of traction motors may be high, it is desirable that the motor current sensors be noncontacting. High-current sensors are commercially available, but tend to be large and costly. According to an aspect of the invention, a noncontacting current sensor having a rated capacity significantly less than the motor (or other) current to be measured is coupled to an electrical conductor for sensing the current in that conductor. The electrical conductor is paralleled by one or more additional similar conductors, so that only a fraction or portion of the current to be measured flows through the conductor associated with the sensor.

Abstract: A transducer probe has a fully populated, integrated, matrix array of acoustical transducers for ultrasound imaging, switchable in real time between two orthogonal 1.5D or 1.75D transducers arrays, consisting of tiled subarrays of transducers which may be switched in real time between vertical and horizontal strip arrays by integrated circuits directly attached to the subarrays, for performing a first level of transmit and receive beam forming functionality with either horizontal or vertical scanning. The integrated circuits include a summer circuit for reducing the output signals of each subarray to a single line, reducing the number of lines required in the cable or connection medium. An interface box mates to a host system and facilitates the switching and control function. Impedance matching in the integrated circuits between transducers and cable lines improves signal transmission in cables. Applications include medical imaging, materials testing and sonar systems.

Abstract: A watchdog monitor coupled to a device bus includes in at least one executable software the ability to produce, during each frame interval, a strobe addressing a predetermined number to the monitor. The monitor responds to the interrupt and to lack of arrival of the correct predetermined number by generating a fault flag. The monitor also runs an internal counter which is reset at each interrupt signal; the count of the internal counter exceeds a threshold count if an interrupt fails to arrive. Such a timed failure results in setting of a frame fault flag. The monitor further runs an internal clock independent of the system clock. A further missing pulse detector initiates a counter at each monitor clock pulse, and raises a flag if the monitor clock counter counts a duration exceeding the monitor inter-clock-pulse interval.

Abstract: An aircraft having a powerplant with an aft-directed main propulsion outlet means for providing forward thrust, and further including duct means having an inlet for receiving at least a proportion of the efflux from said main propulsion outlet and extending forwardly to an auxiliary outlet disposed adjacent or forwardly of the centre of gravity of the aircraft, said auxiliary outlet being arranged to exhaust efflux with at least a vertical component.

Abstract: An oscillator includes an oscillator circuit that receives a control signal having a signal level. The oscillator circuit generates an oscillator signal having a frequency that is proportional to the signal level and that is within a frequency range. A compensation circuit stabilizes the oscillator circuit such that the frequency range includes first and second predetermined frequencies. Thus, such an oscillator can be used to generate an oscillator signal having a first frequency in one application and having a second frequency in another application. The compensation circuit stabilizes the frequency range of the oscillator signal so that it includes the first and second frequencies over broad ranges of operating conditions such as temperature and supply voltage and over broad ranges of component characteristics such as gate dielectric thickness.

Abstract: A number of consecutive samples in unit distance code (here Gray code) are effectively stacked and supplied to respective sum and threshold devices 20 corresponding to each bit position, to determine the bulk property or “generic result” of the consecutive samples. This filtered output is converted back to binary and analogue if required. The digital filter may be used in any of the above applications to “clean” data.

Abstract: A method for manufacturing contacts for a Chalcogenide memory device is disclosed. A via is initially formed within a first oxide layer on a substrate. A conductive layer is then deposited on top of the first oxide layer. A second oxide layer is deposited on the conductive layer. Subsequently, the second oxide layer and the conductive layer are then removed such that the remaining portion of conductive layer within the via flushes with a surface of the first oxide layer. A third oxide layer is deposited on the conductive layer, and the first and second oxide layers. A pattern is formed to remove third layer so that the pattern opens orthgonally across and exposes the conductive layer. Next, a nitride layer is deposited on the third oxide layer, the conductive layer, and the first and second oxide layers. The nitride layer conforms with the contour of the third oxide layer.

Abstract: The invention relates to a method of providing a seal between an aircraft structure (14) and a removable panel (26) mountable on the structure to close an opening (12) therein. According to the invention, the method comprises applying a sealant compound (28) for example a polysulphide rubber compound, to one of the structure and the panel, forming a rebate (46) in the sealant compound, and providing a sealant tape (48) to fit within the rebate. Subsequently, the panel is fastened to the structure with the seal (50) comprising the sealant compound and the sealant tape being sandwiched between the structure and the panel and encircling the opening.

Abstract: A series of processes have been discovered whereby uniform oxygen doping of lead chalcogenides have been achieved by using vapor deposition combined with in situ or ex situ ion implantation allowing the high yield manufacture of high S/N infrared detectors.