Patents Assigned to BANDWIDTH, INC.
  • Publication number: 20040232447
    Abstract: A die carrier for holding a die, such as a microdisplay die, may be electrically connected to a substrate by pressing the substrate against flexible, resilient leads of the die carrier. The package includes a housing and a shroud mounted to the housing. The substrate is inserted through a slot in the shroud and, within the shroud, engages against the flexible, resilient leads, thereby establishing an electrical contact.
    Type: Application
    Filed: June 29, 2004
    Publication date: November 25, 2004
    Applicant: Silicon Bandwidth, Inc.
    Inventors: Stanford W. Crane, Myoung-Soo Jeon, Charley Takeshi Ogata
  • Publication number: 20040222514
    Abstract: A cluster grid array semiconductor die package and mating socket provide electrical connection between one or more semiconductor dies housed within the die package and substrate, such as a printed circuit board, on which the mating socket is mounted. The die package and the mating socket may be easily connected and disconnected. The die package may include power and ground planes built into and distributed within the housing of the die package.
    Type: Application
    Filed: February 20, 2004
    Publication date: November 11, 2004
    Applicant: Silicon Bandwidth, Inc.
    Inventors: Stanford W. Crane, Myoung-soo Jeon, Charley Takeshi Ogata, Ton-Yong Wang, Andreas C. Cangellaris, Jose Schutt-Aine
  • Publication number: 20040203281
    Abstract: A male connector connects with a female connector to establish an electrical connection. The male and female connectors each include a connector housing having hold-down tabs at opposite ends thereof for securing the connector housing to a substrate. The hold-down tabs are staggered or diagonally located such that one hold-down tab is proximal a first side of the connector housing and the other hold-down is proximal a second side of the connector housing. The staggered or diagonally-located hold-down tabs stabilize the connector housing against rocking or other movement on the substrate. The arrangement of hold-down tabs also permits the connector housing to nest or merge with another similarly-designed connector housing. The nested or merged connector housing conserve substrate space and permit a higher density of contacts in a given space on the substrate, whether the space is at an edge or in an interior of the substrate.
    Type: Application
    Filed: January 20, 2004
    Publication date: October 14, 2004
    Applicants: The Panda Project, Inc., Silicon Bandwidth, Inc.
    Inventors: Stanford W. Crane, Lakshminarasimha Krishnapura, Arindum Dutta, Kevin Link
  • Patent number: 6803650
    Abstract: A cluster grid array semiconductor die package and mating socket provide electrical connection between one or more semiconductor dies housed within the die package and substrate, such as a printed circuit board, on which the mating socket is mounted. The die package and the mating socket may be easily connected and disconnected. The die package may include power and ground planes built into and distributed within the housing of the die package.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: October 12, 2004
    Assignee: Silicon Bandwidth Inc.
    Inventors: Stanford W. Crane, Jr., Myoung-soo Jeon, Charley Takeshi Ogata, Ton-Yong Wang, Andreas C. Cangellaris, Jose Schutt-Aine
  • Patent number: 6797882
    Abstract: A die carrier for holding a die, such as a microdisplay die, may be electrically connected to a substrate by pressing the substrate against flexible, resilient leads of the die carrier. The package includes a housing and a shroud mounted to the housing. The substrate is inserted through a slot in the shroud and, within the shroud, engages against the flexible, resilient leads, thereby establishing an electrical contact.
    Type: Grant
    Filed: October 18, 2001
    Date of Patent: September 28, 2004
    Assignee: Silicon Bandwidth, Inc.
    Inventors: Stanford W. Crane, Jr., Myoung-soo Jeon, Charley Takeshi Ogata
  • Publication number: 20040140542
    Abstract: A semiconductor die carrier includes a plurality of electrically insulative side walls; a plurality of electrically conductive leads extending from at least one of the side walls, each of the leads being individually manufactured without use of a lead frame; a semiconductor die positioned such that the electrically conductive leads are disposed at one or more locations around the periphery of the die; and structure for providing electrical connection between the semiconductor die and corresponding ones of the electrically conductive leads.
    Type: Application
    Filed: January 13, 2004
    Publication date: July 22, 2004
    Applicant: Silicon Bandwidth, Inc.
    Inventors: Stanford W. Crane, Maria M. Portuondo
  • Patent number: 6754221
    Abstract: A gateway for communicating telecommunication information between a telecommunication network and customer premises equipment, includes a telecommunication interface, a management module, compression modules, and packetization modules. The telecommunication interface receives telecommunication information from the telecommunication network for communication to the customer premises equipment. The management module determines a bandwidth available to communicate the telecommunication information to the customer premises equipment and selects a compression algorithm according to the available bandwidth. The compression modules compress the telecommunication information using the selected compression algorithm, and the packetization modules generate data packets for communicating the telecommunication information.
    Type: Grant
    Filed: February 15, 2001
    Date of Patent: June 22, 2004
    Assignee: General Bandwidth Inc.
    Inventors: Robert H. Whitcher, David N. Miller, Eric Sean Parham
  • Patent number: 6734546
    Abstract: A micro grid array semiconductor die package includes a housing defining a cavity for holding at least one semiconductor die, said housing including a plurality of insulative side walls, each of said side walls having a bottom surface and an interior wall including a top surface, and an end plate joined to said side walls; and a plurality of substantially straight conductive leads extending through at least one of said side walls, each of said conductive leads including an internal lead section extending into the cavity from the top surface of the interior wall and a external lead section extending externally from said at least one bottom surface of said side wall.
    Type: Grant
    Filed: February 26, 2002
    Date of Patent: May 11, 2004
    Assignee: Silicon Bandwidth, Inc.
    Inventors: Stanford W. Crane, Jr., Vicente D. Alcaria, Myoung-Soo Jeon
  • Patent number: 6709891
    Abstract: A semiconductor die carrier includes a housing that defines a cavity for holding one or more semiconductor dies, electrically conductive leads, and a cover plate having an aperture formed therethrough. The housing includes insulative side walls and a end plate joined to the side walls. The side walls and the end plate may be molded together as a one-piece unit. One or more of the side walls includes openings for receiving the leads so that an internal lead section extends within the cavity and an external lead section extends from the side walls external of the housing. The side walls may include a recess for receiving the cover plate. The aperture in the cover plate allows a semiconductor die held in the housing to be exposed to the environment.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: March 23, 2004
    Assignee: Silicon Bandwidth Inc.
    Inventors: Sanford W. Crane, Jr., Lakshminarasimha Krishnapura, Yun Li
  • Patent number: 6700138
    Abstract: A modular semiconductor die package is provided. The semiconductor die package includes a polymer base for mounting at least one semiconductor die. A polymer cap is operatively secured over the base forming a cavity. The cap includes a light transmissive member operatively positioned to allow light of predetermined wavelengths to pass between at least a portion of the surface of the die and the light transmissive member. A plurality of conductive leads extend through the base to form connections with the semiconductor die(s) positioned in the cavity.
    Type: Grant
    Filed: February 25, 2002
    Date of Patent: March 2, 2004
    Assignee: Silicon Bandwidth, Inc.
    Inventors: Stanford W. Crane, Jr., Jennifer Colegrove, Zsolt Horvath, Myoung-soo Jeon, Joshua Nickel, Lei-Ming Yang
  • Publication number: 20040026757
    Abstract: A modular semiconductor die package is provided. The semiconductor die package includes a polymer base for mounting at least one semiconductor die. A polymer cap is operatively secured over the base forming a cavity. The cap includes a light transmissive member operatively positioned to allow light of predetermined wavelengths to pass between at least a portion of the surface of the die and the light transmissive member. A plurality of conductive leads extend through the base to form connections with the semiconductor die(s) positioned in the cavity.
    Type: Application
    Filed: August 8, 2003
    Publication date: February 12, 2004
    Applicant: Silicon Bandwidth, Inc.
    Inventors: Stanford W. Crane, Jennifer Colegrove, Zsolt Horvath, Myoung-Soo Jeon, Joshua Nickel, Lei-Ming Yang
  • Patent number: 6679733
    Abstract: A male connector connects with a female connector to establish an electrical connection. The male and female connectors each include a connector housing having hold-down tabs at opposite ends thereof for securing the connector housing to a substrate. The hold-down tabs are staggered or diagonally located such that one hold-down tab is proximal a first side of the connector housing and the other hold-down is proximal a second side of the connector housing. The staggered or diagonally-located hold-down tabs stabilize the connector housing against rocking or other movement on the substrate. The arrangement of hold-down tabs also permits the connector housing to nest or merge with another similarly-designed connector housing. The nested or merged connector housing conserve substrate space and permit a higher density of contacts in a given space on the substrate, whether the space is at an edge or in an interior of the substrate.
    Type: Grant
    Filed: December 13, 2001
    Date of Patent: January 20, 2004
    Assignee: Silicon Bandwidth, Inc.
    Inventors: Stanford W. Crane, Jr., Lakshminarasimha Krishnapura, Arindum Dutta, Kevin Link
  • Publication number: 20040007774
    Abstract: A semiconductor die carrier may include an insulative substrate; an array of groups of multiple electrically conductive contacts arranged in rows and columns on the insulative substrate, wherein the groups from adjacent rows are staggered as are the groups from adjacent columns, and a portion of each group overlaps into an adjacent row or an adjacent column of the groups of the array; a semiconductor die; and structure for providing electrical connection between the semiconductor die and the conductive contacts.
    Type: Application
    Filed: June 6, 2003
    Publication date: January 15, 2004
    Applicant: Silicon Bandwidth, Inc.
    Inventors: Stanford W. Crane, Maria M. Portuondo
  • Publication number: 20040010638
    Abstract: A computer system architecture in which functionally compatible electronic components are located on modular printed circuit boards. Thus, a type of processor used by the system can be changed by replacing the printed circuit board incorporating the processor. Similarly a type of peripheral bus used can be changed simply by replacing the printed circuit board containing the peripheral controller. High-density connectors connect the circuit boards. Some embodiments of the invention use a single backplane. Other embodiments place peripheral slots on a second, passive backplane.
    Type: Application
    Filed: April 1, 2003
    Publication date: January 15, 2004
    Applicant: Silicon Bandwidth, Inc.
    Inventor: Stanford W. Crane
  • Patent number: 6663294
    Abstract: Optoelectronic packaging assemblies for optically and electrically interfacing an electro-optical device to an optical fiber and to external circuitry. An optoelectronic packaging assembly includes a submount for holding an optical bench with an electro-optical device. Electrically conductive pins provide electrical contact to the electro-optical device. The optoelectronic packaging assembly includes an optical input receptacle for receiving an optical ferrule and an optical fiber. The optical input receptacle assists optical coupling of the electro-optical device to the optical fiber. The optoelectronic packaging assembly provides for cooling using a heat-sink or a thermal-electric-cooler. Beneficially, the optoelectronic packaging assembly is sealed using a cover.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: December 16, 2003
    Assignee: Silicon Bandwidth, Inc.
    Inventors: Stanford W. Crane, Jr., Zsolt Horvath
  • Publication number: 20030162319
    Abstract: A micro grid array semiconductor die package includes a housing defining a cavity for holding at least one semiconductor die, said housing including a plurality of insulative side walls, each of said side walls having a bottom surface and an interior wall including a top surface, and an end plate joined to said side walls; and a plurality of substantially straight conductive leads extending through at least one of said side walls, each of said conductive leads including an internal lead section extending into the cavity from the top surface of the interior wall and a external lead section extending externally from said at least one bottom surface of said side wall.
    Type: Application
    Filed: February 26, 2002
    Publication date: August 28, 2003
    Applicant: Silicon Bandwidth, Inc.
    Inventors: Stanford W. Crane, Vicente D. Alcaria, Myoung-Soo Jeon
  • Patent number: 6603193
    Abstract: A semiconductor package having a molded body and a plurality of conductive pins that extend from the bottom of the molded body. The semiconductor package further includes a RF shield around a protected cavity that holds a first integrated circuit. The molded body can further include an unprotected plastic cavity for holding a second integrated circuit. The conductive pins form bonding pads that are used to electrically interconnect the first and second semiconductor devices to the external environment. A cover, beneficially comprised of copper, is disposed over the molded body. The plastic cavity beneficially includes a beveled wall that improves the routing of electrical conductors between the first integrated circuit and the second integrated circuit.
    Type: Grant
    Filed: September 6, 2001
    Date of Patent: August 5, 2003
    Assignee: Silicon Bandwidth Inc.
    Inventors: Stanford W. Crane, Jr., Myoung-Soo Jeon, Vicente D. Alcaria
  • Patent number: 6582241
    Abstract: According to one embodiment of the invention, an insertion/extraction apparatus for circuit cards includes a card cage having at least one card guide and at least one channel, at least one circuit card engaged with the card guide, and at least one ejector pivotally coupled to the circuit card. The ejector has protrusions proximate a first end that are operable to engage the channel and a fastener disposed through an aperture in the ejector.
    Type: Grant
    Filed: January 23, 2001
    Date of Patent: June 24, 2003
    Assignee: General Bandwidth Inc.
    Inventor: Ronald D. Lutz, Jr.
  • Patent number: 6577003
    Abstract: A semiconductor die carrier may include an insulative substrate; an array of groups of multiple electrically conductive contacts arranged in rows and columns on the insulative substrate, wherein the groups from adjacent rows are staggered as are the groups from adjacent columns, and a portion of each group overlaps into an adjacent row or an adjacent column of the groups of the array; a semiconductor die; and structure for providing electrical connection between the semiconductor die and the conductive contacts.
    Type: Grant
    Filed: August 1, 2000
    Date of Patent: June 10, 2003
    Assignee: Silicon Bandwidth, Inc.
    Inventors: Stanford W. Crane, Jr., Maria M. Portuondo
  • Patent number: 6574726
    Abstract: A computer system architecture in which functionally compatible electronic components are located on modular printed circuit boards. Thus, a type of processor used by the system can be changed by replacing the printed circuit board incorporating the processor. Similarly a type of peripheral bus used can be changed simply by replacing the printed circuit board containing the peripheral controller. High-density connectors connect the circuit boards. Some embodiments of the invention use a single backplane. Other embodiments place peripheral slots on a second, passive backplane.
    Type: Grant
    Filed: March 28, 2000
    Date of Patent: June 3, 2003
    Assignee: Silicon Bandwidth, Inc.
    Inventor: Stanford W. Crane, Jr.