Patents Assigned to BANDWIDTH, INC.
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Patent number: 6847115Abstract: A packaged semiconductor device that is fabricated with a plurality of conductive leads defined in a strip that beneficially includes a radio frequency shield box. The conductive contacts are located in a housing, beneficially by insert molding or by sandwiching between a bottom piece and a top piece. The housing can further include a cavity that receives a semiconductor device, and the radio frequency shield can receive another semiconductor device. Bonding conductors electrically connect at least one semiconductor device to another semiconductor device and/or to the conductive contacts. A conductive cover is disposed over the housing. The cavity beneficially includes a beveled wall and the conductive leads and the radio frequency shield are beneficially comprised of copper.Type: GrantFiled: September 6, 2001Date of Patent: January 25, 2005Assignee: Silicon Bandwidth Inc.Inventors: Stanford W. Crane, Jr., Myoung-Soo Jeon, Vicente D. Alcaria
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Patent number: 6839342Abstract: A telecommunications network (10) includes a gateway (18) that receives signaling information in a message based signaling format from a Class 5 softswitch (26). The gateway (18) also receives voice traffic over an inter-machine trunk from a public switched telephone network (12). The gateway (18) places the voice traffic into data packets. The gateway (18) transfers the data packets and the signaling information to an Internet Protocol network (30). The data packets and the signaling information may be transferred over a common physical link and over separate logical links.Type: GrantFiled: October 9, 2000Date of Patent: January 4, 2005Assignee: General Bandwidth Inc.Inventors: Eric Sean Parham, Brian E. Williams, Anthony John Paul Carew, Robert Whitcher
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Patent number: 6828511Abstract: A semiconductor die carrier includes a plurality of electrically insulative side walls; a plurality of electrically conductive leads extending from at least one of the side walls, each of the leads being individually manufactured without use of a lead frame; a semiconductor die positioned such that the electrically conductive leads are disposed at one or more locations around the periphery of the die; and structure for providing electrical connection between the semiconductor die and corresponding ones of the electrically conductive leads.Type: GrantFiled: September 28, 2001Date of Patent: December 7, 2004Assignee: Silicon Bandwidth Inc.Inventors: Stanford W. Crane, Jr., Maria M. Portuondo
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Publication number: 20040232447Abstract: A die carrier for holding a die, such as a microdisplay die, may be electrically connected to a substrate by pressing the substrate against flexible, resilient leads of the die carrier. The package includes a housing and a shroud mounted to the housing. The substrate is inserted through a slot in the shroud and, within the shroud, engages against the flexible, resilient leads, thereby establishing an electrical contact.Type: ApplicationFiled: June 29, 2004Publication date: November 25, 2004Applicant: Silicon Bandwidth, Inc.Inventors: Stanford W. Crane, Myoung-Soo Jeon, Charley Takeshi Ogata
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Publication number: 20040222514Abstract: A cluster grid array semiconductor die package and mating socket provide electrical connection between one or more semiconductor dies housed within the die package and substrate, such as a printed circuit board, on which the mating socket is mounted. The die package and the mating socket may be easily connected and disconnected. The die package may include power and ground planes built into and distributed within the housing of the die package.Type: ApplicationFiled: February 20, 2004Publication date: November 11, 2004Applicant: Silicon Bandwidth, Inc.Inventors: Stanford W. Crane, Myoung-soo Jeon, Charley Takeshi Ogata, Ton-Yong Wang, Andreas C. Cangellaris, Jose Schutt-Aine
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Publication number: 20040203281Abstract: A male connector connects with a female connector to establish an electrical connection. The male and female connectors each include a connector housing having hold-down tabs at opposite ends thereof for securing the connector housing to a substrate. The hold-down tabs are staggered or diagonally located such that one hold-down tab is proximal a first side of the connector housing and the other hold-down is proximal a second side of the connector housing. The staggered or diagonally-located hold-down tabs stabilize the connector housing against rocking or other movement on the substrate. The arrangement of hold-down tabs also permits the connector housing to nest or merge with another similarly-designed connector housing. The nested or merged connector housing conserve substrate space and permit a higher density of contacts in a given space on the substrate, whether the space is at an edge or in an interior of the substrate.Type: ApplicationFiled: January 20, 2004Publication date: October 14, 2004Applicants: The Panda Project, Inc., Silicon Bandwidth, Inc.Inventors: Stanford W. Crane, Lakshminarasimha Krishnapura, Arindum Dutta, Kevin Link
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Patent number: 6803650Abstract: A cluster grid array semiconductor die package and mating socket provide electrical connection between one or more semiconductor dies housed within the die package and substrate, such as a printed circuit board, on which the mating socket is mounted. The die package and the mating socket may be easily connected and disconnected. The die package may include power and ground planes built into and distributed within the housing of the die package.Type: GrantFiled: May 31, 2001Date of Patent: October 12, 2004Assignee: Silicon Bandwidth Inc.Inventors: Stanford W. Crane, Jr., Myoung-soo Jeon, Charley Takeshi Ogata, Ton-Yong Wang, Andreas C. Cangellaris, Jose Schutt-Aine
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Patent number: 6797882Abstract: A die carrier for holding a die, such as a microdisplay die, may be electrically connected to a substrate by pressing the substrate against flexible, resilient leads of the die carrier. The package includes a housing and a shroud mounted to the housing. The substrate is inserted through a slot in the shroud and, within the shroud, engages against the flexible, resilient leads, thereby establishing an electrical contact.Type: GrantFiled: October 18, 2001Date of Patent: September 28, 2004Assignee: Silicon Bandwidth, Inc.Inventors: Stanford W. Crane, Jr., Myoung-soo Jeon, Charley Takeshi Ogata
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Publication number: 20040140542Abstract: A semiconductor die carrier includes a plurality of electrically insulative side walls; a plurality of electrically conductive leads extending from at least one of the side walls, each of the leads being individually manufactured without use of a lead frame; a semiconductor die positioned such that the electrically conductive leads are disposed at one or more locations around the periphery of the die; and structure for providing electrical connection between the semiconductor die and corresponding ones of the electrically conductive leads.Type: ApplicationFiled: January 13, 2004Publication date: July 22, 2004Applicant: Silicon Bandwidth, Inc.Inventors: Stanford W. Crane, Maria M. Portuondo
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Patent number: 6754221Abstract: A gateway for communicating telecommunication information between a telecommunication network and customer premises equipment, includes a telecommunication interface, a management module, compression modules, and packetization modules. The telecommunication interface receives telecommunication information from the telecommunication network for communication to the customer premises equipment. The management module determines a bandwidth available to communicate the telecommunication information to the customer premises equipment and selects a compression algorithm according to the available bandwidth. The compression modules compress the telecommunication information using the selected compression algorithm, and the packetization modules generate data packets for communicating the telecommunication information.Type: GrantFiled: February 15, 2001Date of Patent: June 22, 2004Assignee: General Bandwidth Inc.Inventors: Robert H. Whitcher, David N. Miller, Eric Sean Parham
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Patent number: 6734546Abstract: A micro grid array semiconductor die package includes a housing defining a cavity for holding at least one semiconductor die, said housing including a plurality of insulative side walls, each of said side walls having a bottom surface and an interior wall including a top surface, and an end plate joined to said side walls; and a plurality of substantially straight conductive leads extending through at least one of said side walls, each of said conductive leads including an internal lead section extending into the cavity from the top surface of the interior wall and a external lead section extending externally from said at least one bottom surface of said side wall.Type: GrantFiled: February 26, 2002Date of Patent: May 11, 2004Assignee: Silicon Bandwidth, Inc.Inventors: Stanford W. Crane, Jr., Vicente D. Alcaria, Myoung-Soo Jeon
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Patent number: 6709891Abstract: A semiconductor die carrier includes a housing that defines a cavity for holding one or more semiconductor dies, electrically conductive leads, and a cover plate having an aperture formed therethrough. The housing includes insulative side walls and a end plate joined to the side walls. The side walls and the end plate may be molded together as a one-piece unit. One or more of the side walls includes openings for receiving the leads so that an internal lead section extends within the cavity and an external lead section extends from the side walls external of the housing. The side walls may include a recess for receiving the cover plate. The aperture in the cover plate allows a semiconductor die held in the housing to be exposed to the environment.Type: GrantFiled: August 30, 2002Date of Patent: March 23, 2004Assignee: Silicon Bandwidth Inc.Inventors: Sanford W. Crane, Jr., Lakshminarasimha Krishnapura, Yun Li
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Patent number: 6700138Abstract: A modular semiconductor die package is provided. The semiconductor die package includes a polymer base for mounting at least one semiconductor die. A polymer cap is operatively secured over the base forming a cavity. The cap includes a light transmissive member operatively positioned to allow light of predetermined wavelengths to pass between at least a portion of the surface of the die and the light transmissive member. A plurality of conductive leads extend through the base to form connections with the semiconductor die(s) positioned in the cavity.Type: GrantFiled: February 25, 2002Date of Patent: March 2, 2004Assignee: Silicon Bandwidth, Inc.Inventors: Stanford W. Crane, Jr., Jennifer Colegrove, Zsolt Horvath, Myoung-soo Jeon, Joshua Nickel, Lei-Ming Yang
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Publication number: 20040026757Abstract: A modular semiconductor die package is provided. The semiconductor die package includes a polymer base for mounting at least one semiconductor die. A polymer cap is operatively secured over the base forming a cavity. The cap includes a light transmissive member operatively positioned to allow light of predetermined wavelengths to pass between at least a portion of the surface of the die and the light transmissive member. A plurality of conductive leads extend through the base to form connections with the semiconductor die(s) positioned in the cavity.Type: ApplicationFiled: August 8, 2003Publication date: February 12, 2004Applicant: Silicon Bandwidth, Inc.Inventors: Stanford W. Crane, Jennifer Colegrove, Zsolt Horvath, Myoung-Soo Jeon, Joshua Nickel, Lei-Ming Yang
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Patent number: 6679733Abstract: A male connector connects with a female connector to establish an electrical connection. The male and female connectors each include a connector housing having hold-down tabs at opposite ends thereof for securing the connector housing to a substrate. The hold-down tabs are staggered or diagonally located such that one hold-down tab is proximal a first side of the connector housing and the other hold-down is proximal a second side of the connector housing. The staggered or diagonally-located hold-down tabs stabilize the connector housing against rocking or other movement on the substrate. The arrangement of hold-down tabs also permits the connector housing to nest or merge with another similarly-designed connector housing. The nested or merged connector housing conserve substrate space and permit a higher density of contacts in a given space on the substrate, whether the space is at an edge or in an interior of the substrate.Type: GrantFiled: December 13, 2001Date of Patent: January 20, 2004Assignee: Silicon Bandwidth, Inc.Inventors: Stanford W. Crane, Jr., Lakshminarasimha Krishnapura, Arindum Dutta, Kevin Link
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Publication number: 20040007774Abstract: A semiconductor die carrier may include an insulative substrate; an array of groups of multiple electrically conductive contacts arranged in rows and columns on the insulative substrate, wherein the groups from adjacent rows are staggered as are the groups from adjacent columns, and a portion of each group overlaps into an adjacent row or an adjacent column of the groups of the array; a semiconductor die; and structure for providing electrical connection between the semiconductor die and the conductive contacts.Type: ApplicationFiled: June 6, 2003Publication date: January 15, 2004Applicant: Silicon Bandwidth, Inc.Inventors: Stanford W. Crane, Maria M. Portuondo
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Publication number: 20040010638Abstract: A computer system architecture in which functionally compatible electronic components are located on modular printed circuit boards. Thus, a type of processor used by the system can be changed by replacing the printed circuit board incorporating the processor. Similarly a type of peripheral bus used can be changed simply by replacing the printed circuit board containing the peripheral controller. High-density connectors connect the circuit boards. Some embodiments of the invention use a single backplane. Other embodiments place peripheral slots on a second, passive backplane.Type: ApplicationFiled: April 1, 2003Publication date: January 15, 2004Applicant: Silicon Bandwidth, Inc.Inventor: Stanford W. Crane
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Patent number: 6663294Abstract: Optoelectronic packaging assemblies for optically and electrically interfacing an electro-optical device to an optical fiber and to external circuitry. An optoelectronic packaging assembly includes a submount for holding an optical bench with an electro-optical device. Electrically conductive pins provide electrical contact to the electro-optical device. The optoelectronic packaging assembly includes an optical input receptacle for receiving an optical ferrule and an optical fiber. The optical input receptacle assists optical coupling of the electro-optical device to the optical fiber. The optoelectronic packaging assembly provides for cooling using a heat-sink or a thermal-electric-cooler. Beneficially, the optoelectronic packaging assembly is sealed using a cover.Type: GrantFiled: August 29, 2001Date of Patent: December 16, 2003Assignee: Silicon Bandwidth, Inc.Inventors: Stanford W. Crane, Jr., Zsolt Horvath
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Publication number: 20030162319Abstract: A micro grid array semiconductor die package includes a housing defining a cavity for holding at least one semiconductor die, said housing including a plurality of insulative side walls, each of said side walls having a bottom surface and an interior wall including a top surface, and an end plate joined to said side walls; and a plurality of substantially straight conductive leads extending through at least one of said side walls, each of said conductive leads including an internal lead section extending into the cavity from the top surface of the interior wall and a external lead section extending externally from said at least one bottom surface of said side wall.Type: ApplicationFiled: February 26, 2002Publication date: August 28, 2003Applicant: Silicon Bandwidth, Inc.Inventors: Stanford W. Crane, Vicente D. Alcaria, Myoung-Soo Jeon
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Patent number: 6603193Abstract: A semiconductor package having a molded body and a plurality of conductive pins that extend from the bottom of the molded body. The semiconductor package further includes a RF shield around a protected cavity that holds a first integrated circuit. The molded body can further include an unprotected plastic cavity for holding a second integrated circuit. The conductive pins form bonding pads that are used to electrically interconnect the first and second semiconductor devices to the external environment. A cover, beneficially comprised of copper, is disposed over the molded body. The plastic cavity beneficially includes a beveled wall that improves the routing of electrical conductors between the first integrated circuit and the second integrated circuit.Type: GrantFiled: September 6, 2001Date of Patent: August 5, 2003Assignee: Silicon Bandwidth Inc.Inventors: Stanford W. Crane, Jr., Myoung-Soo Jeon, Vicente D. Alcaria