Abstract: A device that is configured to detect spectrally resolved emission from a material is disclosed. The device includes an optical cavity comprising a pair of substrates separated by a distance defined to restrict a photonic density of states (DOS) of the material to be detected, a detector oriented with respect to the optical cavity to receive emission from the optical cavity and a controller configured to control the distance. The pair of substrates includes facing reflective surfaces.

Abstract: The present invention, in some embodiments thereof, relates to inhibitory compositions binding to the ectodomain of a Roundabout (Robo) receptor and to the use of same for downregulating Robo-mediated signaling. In particular, the present invention provides moieties that bind to and prevent dimerization of an Ig-like Robo receptor ectodomain, thereby inhibiting Robo receptor activity.

Abstract: A computer-implemented method for shape deformation, comprising: obtaining an image; obtaining one or more positional constraints; determining a shape deformation/image map, based on the positional constraints; applying the shape deformation to the image; and outputting the image.

Abstract: Disclosed herein is a neural network based pre-decoder comprising a permutation embedding engine, a permutation classifier each comprising one or more trained neural networks and a selection unit. The permutation embedding engine is trained to compute a plurality of permutation embedding vectors each for a respective one of a plurality of permutations of a received codeword encoded using an error correction code and transmitted over a transmission channel subject to interference. The permutation classifier is trained to compute a decode score for each of the plurality of permutations expressing its probability to be successfully decoded based on classification of the plurality of permutation embedding vectors coupled with the plurality of permutations. The selection unit is configured to output one or more selected permutations having a highest decode score. One or more decoders may be then applied to recover the encoded codeword by decoding the one or more selected permutations.

Abstract: Provided are Siglec-based chimeric polypeptides. Accordingly there is provided a chimeric receptor comprising: (a) an extracellular domain comprising an amino acid sequence of a Siglec-7 or a Siglec-9 receptor capable of binding a Siglec-7 and/or a Siglec-9 ligand; and (b) an intracellular domain comprising an amino acid sequence capable of transmitting a co-stimulatory signal in an immune cell expressing the chimeric receptor upon binding of said extracellular domain to said ligand. Also provided are polynucleotides encoding same, cells expressing same and methods of use thereof.

Abstract: There is provided a system for computing a secure statistical classifier, comprising: at least one hardware processor executing a code for: accessing code instructions of an untrained statistical classifier, accessing a training dataset, accessing a plurality of cryptographic keys, creating a plurality of instances of the untrained statistical classifier, creating a plurality of trained sub-classifiers by training each of the plurality of instances of the untrained statistical classifier by iteratively adjusting adjustable classification parameters of the respective instance of the untrained statistical classifier according to a portion of the training data serving as input and a corresponding ground truth label, and at least one unique cryptographic key of the plurality of cryptographic keys, wherein the adjustable classification parameters of each trained sub-classifier have unique values computed according to corresponding at least one unique cryptographic key, and providing the statistical classifier, whe

Abstract: There is provided a computer-implemented method of compressing a baseline dataset, comprising: creating a weight function that calculates a weight for each instance of each unique data elements in the baseline dataset, as a function of sequential locations of each of the instances of each respective unique data element within the baseline dataset, creating an output dataset storing a codeword for each one of the unique data elements, wherein codewords are according to a compression rule defining data elements associated with a relatively higher weight as being associated with codewords that are relatively shorter, dynamically creating the compressed dataset by sequentially iterating, for each current sequential location of the baseline dataset: determining an encoded data element mapped to the respective data element of the current sequential location according to the weight function, and adjusting the codewords of the output dataset according to the current weights to maintain the compression rule.

Abstract: A technique to mitigate timing errors induced by power supply droops includes an inverter-based droop detector as well as Dual Mode Logic (DML) to achieve a droop-resist ant timing response. The droop detector is based on capacitor ratios and is thus less sensitive to Process/Voltage/Temperature (PVT) and to random offset than the prior art. The DML can alter its power/performance ratio based on the droop level input it receives from the detector, such that the critical timings are preserved.

Abstract: A spectral imaging device includes an imager, a scanning stage to establish relative motion between the imager and a sample in a scanning direction and an optical system controlling a light characteristic of a light beam constituting an image of the sample to the imager. The optical system includes a light varying element to receive the light beam and provide an output light beam with spatially varying light characteristic over a cross-section thereof. A set of redirecting optical elements direct light rays from the sample to form the light beam, and to focus the output light beam onto the imager. A controller controls the scanning stage and the imager to capture a plurality of image frames with an overlap including a defined shift that is greater than 1 pixel along the scanning direction between consecutive image frames. A computing device consolidates image data to provide an image of the sample.

Abstract: A logic circuit includes a data signal input, a computational module, a direct timing modulator and an amplitude and non-direct timing modulator. The data signal input inputs data signals. The computational module includes multiple logic elements interconnected to perform a logic function. The direct timing modulator modulates a propagation time of the input data signals from the data signal input to the computational unit, in accordance with a first set of control signals. The amplitude and non-direct timing modulator modulates the processing time of data signals by the computational module and the amplitude of data signals propagating through the computational module, in accordance with a second set of control signals.

Abstract: There is provided a system for computing a secure statistical classifier, comprising: at least one hardware processor executing a code for: accessing code instructions of an untrained statistical classifier, accessing a training dataset, accessing a plurality of cryptographic keys, creating a plurality of instances of the untrained statistical classifier, creating a plurality of trained sub-classifiers by training each of the plurality of instances of the untrained statistical classifier by iteratively adjusting adjustable classification parameters of the respective instance of the untrained statistical classifier according to a portion of the training data serving as input and a corresponding ground truth label, and at least one unique cryptographic key of the plurality of cryptographic keys, wherein the adjustable classification parameters of each trained sub-classifier have unique values computed according to corresponding at least one unique cryptographic key, and providing the statistical classifier, whe

Abstract: An FD-SOI GC-edRAM gain cell includes: a write bit line terminal connected to a WBL; a read bit line terminal connected to a RBL; a write trigger terminal connected to a WWL, for inputting a write trigger signal; a read trigger terminal put connected to a RWL, for inputting a read trigger signal; at least one body voltage terminal connected to a respective body voltage; and multiple FD-SOI transistors. The FD-SOI transistors are interconnected to form a storage node for retaining a data signal. The bodies of at least two of the transistors are coupled in a single well to a body voltage terminal. The write trigger signal triggers writing an input data signal from the write bit line terminal to the storage node and the read trigger signal triggers outputting the retained data signal from the storage node to the read bit line terminal.

Abstract: There is provided a computer-implemented method of compressing a baseline dataset, comprising: creating a weight function that calculates a weight for each instance of each unique data elements in the baseline dataset, as a function of sequential locations of each of the instances of each respective unique data element within the baseline dataset, creating an output dataset storing a codeword for each one of the unique data elements, wherein codewords are according to a compression rule defining data elements associated with a relatively higher weight as being associated with codewords that are relatively shorter, dynamically creating the compressed dataset by sequentially iterating, for each current sequential location of the baseline dataset: determining an encoded data element mapped to the respective data element of the current sequential location according to the weight function, and adjusting the codewords of the output dataset according to the current weights to maintain the compression rule.

Abstract: A FinFET gain cell includes a write port, read port and storage node. The write port includes at least one write FinFET transistor and has write word-line (WWL) and write bit-line (WBL) inputs. The read port includes at least one FinFET read transistor and has a read word-line (RWL) input and a read bit-line (RBL) output. The storage node stores a data level written from said WBL. The storage nodes includes a single layer interconnect which connects the write port output diffusion connection to the read port input gate connection. The height of the single layer interconnect at the write port output diffusion connection is different from the height of the single layer interconnect at the read port input gate connection.

Abstract: This disclosure relates to methods of treating or preventing cystic fibrosis transmembrane conductance regulator (CFTR) mediated diseases such as cystic fibrosis, chronic obstructive pulmonary disease, chronic pancreatitis, chronic bronchitis, asthma, mucus formation, comprising administering an effective amount of a 2-amino-N?-benzylidene-acetohydrazide compound or derivative thereof to a subject in need thereof. In certain embodiments, the 2-amino-N?-benzylidene-acetohydrazide compound is ((E)-N?-(3,5-dibromo-2,4-dihydroxybenzylidene)-2-(m-tolylamino)acetohydrazide; or (E)-N?-(3,5-dibromo-2,4-dihydroxybenzylidene)-2-(p-tolylamino)acetohydrazide.

Abstract: An FD-SOI GC-edRAM gain cell includes: a write bit line terminal connected to a WBL; a read bit line terminal connected to a RBL; a write trigger terminal connected to a WWL, for inputting a write trigger signal; a read trigger terminal put connected to a RWL, for inputting a read trigger signal; at least one body voltage terminal connected to a respective body voltage; and multiple FD-SOI transistors. The FD-SOI transistors are interconnected to form a storage node for retaining a data signal. The bodies of at least two of the transistors are coupled in a single well to a body voltage terminal. The write trigger signal triggers writing an input data signal from the write bit line terminal to the storage node and the read trigger signal triggers outputting the retained data signal from the storage node to the read bit line terminal.

Abstract: A logic circuit includes a data signal input, a computational module, a direct timing modulator and an amplitude and non-direct timing modulator. The data signal input inputs data signals. The computational module includes multiple logic elements interconnected to perform a logic function. The direct timing modulator modulates a propagation time of the input data signals from the data signal input to the computational unit, in accordance with a first set of control signals. The amplitude and non-direct timing modulator modulates the processing time of data signals by the computational module and the amplitude of data signals propagating through the computational module, in accordance with a second set of control signals.

Abstract: A device that is configured to detect spectrally resolved emission from a material is disclosed. The device includes an optical cavity comprising a pair of substrates separated by a distance defined to restrict a photonic density of states (DOS) of the material to be detected, a detector oriented with respect to the optical cavity to receive emission from the optical cavity and a controller configured to control the distance. The pair of substrates includes facing reflective surfaces.

Abstract: A FinFET gain cell includes a write port, read port and storage node. The write port includes at least one write FinFET transistor and has write word-line (WWL) and write bit-line (WBL) inputs. The read port includes at least one FinFET read transistor and has a read word-line (RWL) input and a read bit-line (RBL) output. The storage node stores a data level written from said WBL. The storage nodes includes a single layer interconnect which connects the write port output diffusion connection to the read port input gate connection. The height of the single layer interconnect at the write port output diffusion connection is different from the height of the single layer interconnect at the read port input gate connection.

Abstract: A CDMR memory cell, includes a first bitcell which is used to store a current data level and a second bitcell which is used to store the complementary data level. When a read operation is performed, a comparator compares the data levels read from the two bitcells. If these two levels are not complementary, the comparator outputs an indicator. This indicator serves as an alert that a storage error has, or may have, occurred.