Abstract: In an embodiment of the invention, a method is presented to operationally integrate one or more RAID control mechanisms into a flash electronic disk controller. The method includes incorporating one or more RAID features into a flash electronic disk by adding one or more RAID components in a flash controller, wherein the flash electronic disk includes a RAID control module to control the one or more RAID components; receiving a read or write operation command at a flash controller from a host; translating the read or write operation command into a command format understood by one or more flash controllers; translating the command format into an instruction format understood by one or more flash memory devices; and accessing one or more memory locations in the one or more flash memory devices according to the instruction format to perform a read or write operation for the host.

Abstract: In an embodiment of the invention, a method comprises: requesting an update or modification on a control data in at least one flash block in a storage memory; requesting a cache memory; replicating, from the storage memory to the cache memory, the control data to be updated or to be modified; moving a clean cache link list to a dirty cache link list so that the dirty cache link list is changed to reflect the update or modification on the control data; and moving the dirty cache link list to a for flush link list and writing an updated control data from the for flush link list to a free flash page in the storage memory.

Abstract: In one embodiment of the invention, a system architecture for bus masters and bus arbiters are provided to support routing and failover. The system comprises large pools of bus masters, a plurality of sets can be configured to control a plurality of slave devices wherein each set contains a collection of bus masters attached to central arbiter driving one of the system buses. Each set controls a group(s) of slave device that are primarily controlled by the bus master(s) within the set. Hence, a system can therefore include of a plurality of sets and can control a group of slave devices.

Abstract: A hybrid storage system is described having a mixture of different types of storage devices comprising rotational drives, flash devices, SDRAM, and SRAM. The rotational drives are used as the main storage, providing lowest cost per unit of storage memory. Flash memory is used as a higher-level cache for rotational drives. Methods for managing multiple levels of cache for this storage system is provided having a very fast Level 1 cache which consists of volatile memory (SRAM or SDRAM), and a non-volatile Level 2 cache using an array of flash devices. It describes a method of distributing the data across the rotational drives to make caching more efficient. It also describes efficient techniques for flushing data from L1 cache and L2 cache to the rotational drives, taking advantage of concurrent flash devices operations, concurrent rotational drive operations, and maximizing sequential access types in the rotational drives rather than random accesses which are relatively slower.

Abstract: In an embodiment of the invention, a method which speeds up the transfer of data and increases the data throughput in an IO network comprised of Host Bus Adapters (HBAs)/IO bridges-switches, IO devices, and hosts is described. In the embodiment of the present invention, HBAs and IO bridges-switches utilize a multi-level cache composed of volatile memories (such as SRAM, SDRAM, etc.) and solid-state memories (such as flash, MRAM, etc.). These memories are used to cache the most recently accessed IO data by an active host or by another HBA/IO bridge-switch. Cache content can be from the local IO devices (the ones connected directly to the HBA/IO bridge-switch), from remote IO devices (the ones connected to different HBA/IO bridges/switches), or from both (a portion from local IO devices and another portion from remote IO devices). The combination of these caches from different HBAs/IO bridges-switches creates the cache for all IO devices in the entire network.

Abstract: In an embodiment of the invention, a method comprises: A method, comprising: issuing, by a Direct Memory Access (DMA) engine, an update request to a dependency table if the DMA engine has finished executing a first descriptor; and issuing, by the DMA engine, a monitoring request if the DMA engine is executing a second descriptor that depends on a completion of a data transfer so that the DMA engine can monitor a status of a selected subindex related to the data transfer, wherein the subindex is in the dependency table.

Abstract: The present invention pertains to a hard disk drive form factor compatible solid-state storage device enclosure assembly that protects circuit boards contained within the enclosure from environmental disruption, such as mechanical stress, vibration, external electronic disruption, or any combination of these, while allowing for a variable number of circuit boards in the SSD enclosure. In another embodiment, the solid-state storage device enclosure assembly, or a similar circuit board assembly, includes an alignment guide that precludes a circuit board from being misaligned within the enclosure.

Abstract: In an embodiment of the invention, a method for to use a two level linked list descriptor mechanism to pass information among flash, memory, and IO controller modules is presented. The method includes creating a first level data structure for one or more first level descriptors; creating a second level data structure for one or more second level descriptors, each second level descriptor having a pointer to tracking information that includes start information, running information, and rewind information for a data DMA; using the one or more second level descriptors, the one or more first level descriptors, and the tracking information for a data DMA; updating the tracking information during the data DMA; and updating the tracking information at the end of the data DMA.

Abstract: A solution for reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device is disclosed.

Abstract: A hybrid storage system is described having a mixture of different types of storage devices comprising rotational drives, flash devices, SDRAM, and SRAM. The rotational drives are used as the main storage, providing lowest cost per unit of storage memory. Flash memory is used as a higher-level cache for rotational drives. Methods for managing multiple levels of cache for this storage system is provided having a very fast Level 1 cache which consists of volatile memory (SRAM or SDRAM), and a non-volatile Level 2 cache using an array of flash devices. It describes a method of distributing the data across the rotational drives to make caching more efficient. It also describes efficient techniques for flushing data from L1 cache and L2 cache to the rotational drives, taking advantage of concurrent flash devices operations, concurrent rotational drive operations, and maximizing sequential access types in the rotational drives rather than random accesses which are relatively slower.

Abstract: A built-in self test (BIST) circuit and method is provided to test a first and a second DLL. The first DLL has a first delay input, a first clock input disposed to receive a clock input signal, and a first clock output that provides a first clock output signal delayed in comparison with the clock input signal. The second DLL has a second delay input, a second clock input disposed to receive the clock input signal, and a second clock output signal delayed in comparison with the clock input signal. The BIST circuitry provides a first delay amount over the first delay input creating a start offset between the first and second clock output signals. If the first DLL is functioning properly the start offset between the output signals should remain unchanged even after the BIST circuitry provides an additional common delay amount to the first and second delay inputs.

Abstract: The invention provides the data flow communication control between the source (flash/IO) and destination (IO/flash) cores. The source and destination cores are started simultaneously instead of serially and get instructions from the descriptors provided and set-up by the processor. Each source and destination core's descriptors1 are correlated or tied with each other by the processor by providing information to the hardware assist mechanism. The hardware assist mechanism responsible for moderating the data transfer from source to destination. The flow tracker guarantees that data needed by destination exists. 1 Descriptors are set of instructions that is used to activate the DMA controller. By applying the invention to the prior approach/solution, the data latency between the flash & IO bus will be reduced. Processor interrupts will be minimized while data transfer between the flash & IO bus is ongoing.

Abstract: The present invention relates to an apparatus, method, and/or sequence that adaptively provide the recovery of data after a power cycle sequence, wherein only minimal updates are provided for control blocks associated with the data.

Abstract: The present invention pertains to a multi-profile memory controller and devices that use multi-profile memory controllers. More particularly, the present invention pertains to a multi-profile memory controller and related methods and systems that can operate with memory locations, memory devices, or both which are associated with different memory attributes, different attribute qualifiers, or the like, while minimizing or avoiding some or all of the disadvantages of the prior art.

Abstract: A solution for reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device is disclosed.

Abstract: Embodiments of the present invention relate to an apparatus, method, and/or sequence for a distributed ECC that may be used in a storage system. In another embodiment of the invention, an apparatus for handling distributed error correction code (ECC) operations, includes: a plurality of ECC engines configured to perform ECC operations in parallel on multiple data parts; the plurality of ECC engines distributed in parallel to receive some of the multiple data parts that are read from storage media devices and to receive some of the other multiple data parts that are to be written to the storage media devices; and the plurality of ECC engines configured to use respective ECC bytes corresponding to respective ones of the multiple data parts.

Abstract: A solution for performing reduced latency memory read transactions is disclosed. In one example, a storage apparatus has a memory array that includes: a flash device having a data register, a memory interface coupled to the memory array and a buffer set that includes at least one buffer suitable for use as a prefetch buffer. The memory interface, in response to a memory read transaction request, performs a read operation and, if stored data exists within the memory array that meets a prefetch selection criterion, also performs an internal read operation. The internal read operation includes allocating a prefetch buffer in the buffer set and storing the data as prefetch data in the prefetch buffer. If the memory interface receives a second memory read transaction request for data that is currently available as prefetch data, the memory interface responds by performing a forwarding transaction that includes retrieving the prefetch data from the prefetch buffer and forwarding the prefetch data to a host.

Abstract: The present invention relates to a multilevel memory bus system for transferring information between at least one DMA controller and at least one solid-state semiconductor memory device, such as NAND flash memory devices or the like. This multilevel memory bus system includes at least one DMA controller coupled to an intermediate bus; a flash memory bus; and a flash buffer circuit between the intermediate bus and the flash memory bus. This multilevel memory bus system may be disposed to support: an n-bit wide bus width, such as nibble-wide or byte-wide bus widths; a selectable data sampling rate, such as a single or double sampling rate, on the intermediate bus; a configurable bus data rate, such as a single, double, quad, or octal data sampling rate; CRC protection; an exclusive busy mechanism; dedicated busy lines; or any combination of these.

Abstract: A solution for reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device is disclosed.

Abstract: The present invention pertains to a hard disk drive form factor compatible solid-state storage device enclosure assembly that protects circuit boards contained within the enclosure from environmental disruption, such as mechanical stress, vibration, external electronic disruption, or any combination of these, while allowing for a variable number of circuit boards in the SSD enclosure. In another embodiment, the solid-state storage device enclosure assembly, or a similar circuit board assembly, includes an alignment guide that precludes a circuit board from being misaligned within the enclosure.