Abstract: The present invention pertains to a method of writing test data in a memory space within a memory store and includes: generating a header having an address representing the location of the memory space in the memory store, and a seed value; generating test data using the seed value; and storing the header and the test data in the memory space. Another embodiment of the present invention pertains to a method of testing a memory space within a memory store that includes: generating a header having an address representing the location of the memory space in the memory store, and a seed value; generating a set of values using the seed value; storing the header and the set of values in the memory space; retrieving data from the memory space; generating a new seed value using the set of values; and comparing the new seed value with the seed value.
Abstract: An apparatus for and method of memory operation having a memory, a cache containing a plurality of entries with a plurality of the entries to be written to memory, a detector for detecting in the cache the plurality of entries to be written to memory, and a processor for erasing a first portion of the memory to accommodate the plurality of entries to be written to memory and writing to the first portion of the memory the plurality of entries to be written to memory wherein an erase operation is followed by a plurality of sequential write operations.
Abstract: An improved printed circuit board assembly is disclosed. The printed circuit board assembly comprises a first plate, a second plate attachably coupled to the first plate, and at least one printed circuit board sandwiched between the first plate and the second plate, the at least one printed circuit board extending over the entire area of the first and second plate. By utilizing an assembly in accordance with the present invention, the available space on each of the plurality of printed circuit boards is maximized. By maximizing the available space, more electronic circuitry can be incorporated onto the board. Furthermore, the exterior spacer design together with interior spacer elements firmly secures each printed circuit board while maintaining a constant separation between each board.
Type:
Grant
Filed:
February 15, 2000
Date of Patent:
November 13, 2001
Assignee:
BiTMICRO NETWORKS, Inc.
Inventors:
Roland F. Portman, Edgar Jhay Gregorios