Abstract: A test head performs at-speed testing of high serial pin count gigabit per second (GBPS) devices. The test head includes a device under test (DUT) coupled to a first portion of the test head and a rider board coupled to the DUT. The rider board includes a first signal path including switching matrices coupled to the DUT, a second signal path including bit error rate testing (BERT) engines, each of the BERT engines being coupled to each other, corresponding ones of the switching matrices, and to the DUT, and a third signal path including Ethernet testing circuits coupled to the DUT. The BERT engines allow for routing of a test signal from any of the switching matrices to any other switching matrix (e.g., between non-adjacent switching matrices).

Abstract: The system and method for adaptive flow control transmits pause off packets to network nodes after a calculated time based on switch resource usage thereby alleviating congestion is a network switching system. The method includes measuring a resource usage level in a network switching system, incrementing a register based on the measurement if the measurement exceeds a predetermined level, decrementing the register at a constant rate, and generating a pause off packet when the register is decremented to or below a pre-specified level.

Abstract: A method and system for processing a data flow in a multi-channel, multi-service environment is described. In one embodiment, a socket is dynamically allocated, the socket including a dynamically allocated service. Further, the server processes the data flow based upon the type of data being processed.

Abstract: A system and method for continual cable thermal monitoring using cable resistance considerations for Power over Ethernet (PoE) applications. Cable heating in PoE applications is related to the resistance of the cable itself. By periodically monitoring the resistance of the cable, it can be determined whether the cable has exceeded certain operating thresholds. The determined resistance as a proxy for cable heating can then be used in adjusting operational characteristics of PoE channels.

Abstract: A method and system to transfer a data stream from a data source to a data sink are described herein. The system comprises a trigger core, a plurality of dedicated buffers and a plurality of dedicated buses coupled to the plurality of buffers, trigger core, the data source and the data sink. In response to receiving a request for a data transfer from a data source to a data sink, the trigger core assigns a first buffer and a first bus to the data source for writing data, locks the first buffer and first bus, releases the first buffer and the first bus upon indication from the data source of completion of data transfer to the first buffer, assigns the first buffer and first bus to the data sink for reading data and assigns a second buffer and second bus to the data source for writing data thereby pipelining the data transfer from the data source to the data sink.

Abstract: Systems, methods, and computer program products that can be used concurrently or alternatively to detect errors in data as well as to protect access to data are provided. Embodiments enable a coherent data set (CDS) which is a data set guaranteed to be genuine and error-free at run-time. Embodiments provide systems, methods, and computer program programs to create a CDS, identify a CDS, and verify the coherency of a data set purported to be a CDS. Embodiments further enable privileged functions which are functions that can only be accessed by a restricted set of other privileged functions. Embodiments provide systems, methods, and computer program products to create, identify, and protect access to privileged functions.

Abstract: A method to detect an event between a data source and a data sink using a trigger core is described herein. The method comprises monitoring control lines and an associated data stream for a programmable pattern, wherein the pattern is one or more of a condition, state or event. The method further comprises generating an indication by updating a status register, sending an interrupt or asserting a control line upon a pattern match.

Abstract: A method and system to transfer data from one or more data sources to one or more data sinks using a pipelined buffer interconnect fabric is described.

Abstract: A phase rotator generates an output signal having plurality of possible output phases with reduced phase jitter. The low jitter phase rotator includes a plurality of differential amplifiers configured to receive a plurality of input differential signals having different phases, and configured to generate a plurality of weighted signals responsive to the plurality of input differential signals. A plurality of digital-to-analog converters (DAC) are arranged into a plurality of groups, each group of DACs configured to provide current for one of the corresponding differential amplifiers. The number of active DACs in each group of DACs determines a relative weighting of the weighted signals, where relative weighting determining an output phase of an output signal of the phase rotator. The DACs are configured to adjust the output phase of the phase rotator. At a kth phase, N/4 adjacent DACs are activated that are indexed as m0, m1, . . . m((N/4)?1), wherein N is the number of said plurality of DACs.

Abstract: A MIMO transceiver integrated circuit (IC) includes a plurality of multiple band direct conversion transmitter sections, a plurality of multiple band direct conversion receiver sections, and a local oscillation generation module. Each of the plurality of multiple band direct conversion transmitter sections includes a transmit baseband module and a multiple frequency band transmission module. Each of the plurality of multiple band direct conversion receiver sections includes a multiple frequency band reception module and a receiver baseband module. The local oscillation generation module is operably coupled to generate the first frequency band local oscillation when the multiple band MIMO transceiver IC is in a first mode and operably coupled to generate the second frequency band local oscillation when the multiple band MIMO transceiver IC is in a second mode.

Abstract: A computer program product comprising a computer useable medium including control logic stored therein to transfer data from a data source to a data sink is described herein.

Abstract: Systems, methods, and computer program products that can be used concurrently or alternatively to detect errors in data as well as to protect access to data are provided. Embodiments enable a coherent data set (CDS) which is a data set guaranteed to be genuine and error-free at run-time. Embodiments provide systems, methods, and computer program programs to create a CDS, identify a CDS, and verify the coherency of a data set purported to be a CDS. Embodiments further enable privileged functions which are functions that can only be accessed by a restricted set of other privileged functions. Embodiments provide systems, methods, and computer program products to create, identify, and protect access to privileged functions.

Abstract: A method for synchronizing clocks in a packet transport network. The method comprises, receiving an external network clock at a central packet network node and transmitting timing information to a plurality of packet network devices, the timing information based upon the external network clock. The method further comprises, transmitting and receiving data that is synchronized to the timing information to a plurality of connected packet network devices. And finally, delivery of packets to an external interface via a packet network that contains data synchronized to the external network clock.

Abstract: A microprocessor system architecture is disclosed which allows for the selective execution of programmed ROM microcode or, alternatively, RAM microcode if there has been a correction or update made to the ROM microcode originally programmed into the system. Patched or updated RAM microcode is utilized or executed only to the extent of changes to the ROM microcode, otherwise the ROM microcode is executed in its normal fashion. When a patch is received, it is loaded into system RAM along with instructions or other appropriate signals to direct the execution of the patched or updated microcode from RAM instead of the existing ROM microcode. Various methods are presented for selecting the execution of the appropriate microcode depending upon whether there have been changes made to it.

Abstract: A low pass filter includes a switchable resistor bank, a gain stage, and a capacitor bank. The resistors and capacitors switched into the circuit determine a cutoff frequency of the low pass filter. Frequency programmability may be obtained using the switchable resistor bank implemented as a parallel bank of binary weighted resistors. Further frequency programmability may be obtained using the switchable capacitor bank in conjunction with the switchable resistor bank. The resistor and capacitor processes in a semiconductor wafer are sufficiently accurate and repeatable so as to minimize any necessary calibration.

Abstract: One or more methods and systems of effectively retrieving data stored in a media of a storage device are presented. The one or more methods and systems are implemented by way of correcting and detecting errors using a multi-stage decoding process. In one embodiment, the storage device comprises a magnetic hard drive. In one embodiment, the system and method applies an encoding/decoding technique that allows error correction and detection to be performed over a number of successive decode stages or processing stages. Use of the system and method increases the maximum number of symbol errors that may be corrected in an encoded codeword, providing an improvement in data recovery.

Abstract: A method for forming and packaging an integrated circuit having a plurality of circuit components on a semi conductive substrate die. The plurality of circuit components include at least one active component that operates on an information signal, a tuning node coupled to the at least one active component, an Electro Static Discharge (ESD) protection inductor, and a chip pad. The chip pad couples to the tuning node. The ESD protection inductor communicatively couples between the tuning node and a rail formed on the semi conductive substrate die. The ESD protection inductor provides ESD protection prior to packaging of the semi conductive substrate die or in some cases prior to the installation of the packaged die on a PC board or the equivalent. The bond wire couples between the chip pad and a package pad and serves as a tuning inductor for the circuit.

Abstract: A system and method for determining phase of a subcarrier (e.g., a jittering video subcarrier). Various aspects of the present invention may comprise determining at least one weighting factor based, at least in part, on a subcarrier synchronization signal (e.g., a video synchronization signal). A first subcarrier phase sample and at least a second subcarrier phase sample may then be obtained. Subcarrier phase may then be determined by interpolating between the first subcarrier phase sample and the second subcarrier phase sample, where such interpolation (e.g., linear interpolation) may be based, at least in part, on the determined weighting factor(s).

Abstract: Systems and methods that handle frames in multiple stack environments are provided. In one embodiment, a system may include, for example, a non-offload protocol stack and an offload protocol stack, the offload protocol stack being coupled to the non-offload protocol stack. The non-offload protocol stack may include, for example, one or more partially processed frames. The one or more partially processed frames may be sent to the offload protocol stack to complete processing in the offload protocol stack.

Abstract: A supervisory communications device, such as a headend device within a cable communications network, monitors and controls communications with a plurality of remote communications devices, such as cable modems, throughout a widely distributed network. The supervisory device allocates bandwidth on the upstream channels by sending MAP messages over its downstream channel. A master-slave interface permits a second supervisory device to be connected to increase the number of available upstream channels. When one device operates as the slave device to the other, the slave device is programmable to select MAP messages from either of the master device or the slave device. A primary filter and a slave filter are provided to specify which downstream channel(s) has the authority to issue MAP messages for each available upstream channel. The filters utilizes registers to authenticate the source of the MAP messages.