Abstract: A RF receiver includes a low noise amplifier and blocking module, a down conversion module, and a local oscillation module. The low noise amplifier and blocking module is coupled to receive an inbound RF signal, wherein the amplified inbound RF signal includes a desired RF signal component and a blocking RF signal component; attenuate the blocking RF signal component of the amplified inbound RF signal; and pass, substantially unattenuated and amplified, the desired RF signal component of the inbound RF signal to produce a desired inbound RF signal. The down conversion module is coupled to convert desired inbound RF signal into an inbound signal based on a receive local oscillation. The local oscillation module is coupled to produce the receive local oscillation, wherein the local oscillation module includes a notch filter module coupled to attenuate signal components of the receive local oscillation at frequencies corresponding to harmonics of the blocking RF signal component.

Abstract: A low-complexity sampling rate conversion (SRC) method and apparatus for the processing of digital audio signals. A first stage upsamples an input audio signal to generate an upsampled audio signal. For example, the first stage may perform 1:2 upsampling using a halfband filter. A second stage re-samples the upsampled audio signal from the first stage at a target sampling rate. For example, re-sampling may be achieved using linear interpolation.

Abstract: A system and method are presented for changing physical layer (PHY) parameters in a PHY device of a communications system. New parameters are written to a first-in first-out queue in a serial interface, while the scheduled time for the changeover is written to a control register in the serial interface. When the time for the changeover occurs, the parameters are written to the PHY device via a port of the serial interface.

Abstract: The programmable slew rate driver uses separate and programmably selectable resistors for time constants for on and off transitions on the NMOS and PMOS output transistors. By proper setting of gate voltage time constants and overlap of NMOS and PMOS “on” times, a desired output slew rate is accomplished, having a smooth output transition, without generation of shoot-through current. The programmable slew rate driver includes a first driver transistor coupled between the first supply voltage and output, a second driver transistor coupled between the second supply voltage and output, a plurality of upper transition blocks coupled in parallel and a plurality of lower transition blocks coupled in parallel between the first and second supply voltage. The rates of change and overlap of the gate voltages are in turn substantially determined by the resistance of the lower transition control blocks and the capacitance of the gate of the second driver transistor.

Abstract: A method and apparatus for performing trellis coded modulation of signals for transmission on a TDMA channel of a cable network, such as a DOCSIS cable network, is provided. In an embodiment, an upstream modulator portion of a cable modem receives burst data, selectively encodes the burst data for trellis coded modulation to generate encoded symbols, and modulates the encoded symbols for selective transmission over a time division multiple access (TDMA) channel or a synchronous code division multiple access (S-CDMA) channel of the cable network.

Abstract: A system, method, and apparatus for dynamically booting processor code memory with a wait instruction is presented herein. A wait instruction precedes the transfer of a new code portion to the code memory. The wait instruction causes the processor to temporarily cease using the code memory. When the processor ceases using the code memory, the processor signals a direct memory access (DMA) module to transfer a new code portion to the code memory. The DMA module transfers the new code portion to the code memory and transmits a signal to the processor when the transfer is completed. The signal causes the processor to resume. When the processor resumes, the processor begins executing the instructions at the next code address.

Abstract: An apparatus and method to use a single voltage controlled oscillator (VCO) to generate frequencies to cover multiple frequency bands. The single VCO generates local oscillator signals for more than one frequency band of a communication standard or protocol, such as the IEEE 802.11 standard.

Abstract: A phase rotator generates an output signal having plurality of possible output phases with reduced phase jitter. The low jitter phase rotator includes a plurality of differential amplifiers configured to receive a plurality of input differential signals having different phases, and configured to generate a plurality of weighted signals responsive to the plurality of input differential signals. A plurality of digital-to-analog converters (DAC) are arranged into a plurality of groups, each group of DACs configured to provide current for one of the corresponding differential amplifiers. The number of active DACs in each group of DACs determines a relative weighting of the weighted signals, where relative weighting determining an output phase of an output signal of the phase rotator. The DACs are configured to adjust the output phase of the phase rotator. At a kth phase, N/4 adjacent DACs are activated that are indexed as m0, m1, . . . m((N/4)?1), wherein N is the number of said plurality of DACs.

Abstract: A scheme for PLL-based at-speed scan testing in which a clock generation circuit is used to generate different clock signals to scannable flip-flops of an integrated circuit. When the integrated circuit is under at-speed scan test mode of operation, the clock generation circuit receives a scan-clock signal to scan in a test vector to the scannable flip-flops during an input shift phase when shifting is enabled and to scan out a resultant vector from the scannable flip-flops during an output shift phase when shifting is also enabled. However, when shifting is not enabled during a capture phase between the two shift phases, the scan-clock signal triggers a 2-pulse circuit to release two pulses during the capture phase of at-speed scan testing. The two pulses from the 2-pulse circuit are based on an internal PLL-based clock signal. The clock generation circuit may be utilized in single or multiple clock domain systems.

Abstract: A system and method is presented to utilize hardware instead of software to compare for bandwidth request changes between two consecutively received unsolicited grant service (UGS) extended headers for the same service identifier (SID), obtains significant savings in CPU cycles for the CMTS software. The system determines whether adequate bandwidth is being provided from a cable modem termination system to a data provider during a unsolicited grant service flow. The system includes a means for receiving a current voice packet in the unsolicited grant service flow at the cable modem termination system from the data provider, where the current voice packet comprises a unsolicited grant service extended header. The system further includes means for comparing the current unsolicited grant service extended header with a previous unsolicited grant service extended header.

Abstract: A processing device includes one or more resources, a plurality of peripheral bus interfaces that support resource sharing with a plurality of other processing devices, a primary routing resources and a node ID register. The primary routing resources are programmable with a plurality of address ranges. The processing device is operable to determine a routing of peripheral bus transactions among the plurality of peripheral bus interfaces based upon a destination address of the peripheral bus transaction and primary routing resources contents. The node ID register is programmable with a plurality of override indications. The processing device is operable to determine an override routing of peripheral bus transactions among the plurality of peripheral bus interfaces based upon a destination node ID of the peripheral bus transaction and node ID register contents.

Abstract: A wireless device and system employs a two-dimensional (2-D) Trellis code that can be applied to Quadrature Phase Shift Keying (QPSK) and higher order Quadrature Amplitude Modulation (QAM) constellations. The Trellis codes employed have optimal Euclidean distance properties for QPSK constellations, and have very good Euclidean distance properties for higher-order QAM constellations. The Trellis codes are suited for transmission systems that adopt multi-mode QPSK and QAM constellations with different data rates since the same Trellis code can be applied to all modulation formats and the same decoder can be used at the receiver for all modulation formats. Modulation formats include QPSK, 8-QAM, 16-QAM, 32-QAM, and 64-QAM and may be extended to even higher order modulations formats.

Abstract: A transcoder (10) and a decoder (80) reconstruct an image from still image compressed data, such as EXIF data. The transcoder transcodes the still image compressed data into a bit stream of moving picture compressed data, such as an MPEG-2 4:2:2P bit stream with only intra pictures. The decoder (80) decodes the bit stream of moving picture compressed data into a still picture image that can be stored in a digital memory (100).

Abstract: A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(l,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, error-tolerant sync mark detection, and the ability to recover data when the sync mark is obliterated allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery.

Abstract: A Radio Frequency (RF) receiver includes a low noise amplifier (LNA) and a mixer coupled to the output of the LNA. The gain of the LNA is adjusted to maximize signal-to-noise ratio of the mixer and to force the mixer to operate well within its linear region when an intermodulation interference component is present. The RF receiver includes a first received signal strength indicator (RSSI_A) coupled to the output of the mixer that measures the strength of the wideband signal at that point. A second received signal strength indicator (RSSI_B) couples after the BPF and measures the strength of the narrowband signal. The LNA gain is set based upon these signal strengths. By altering the gain of the LNA by one step and measuring the difference between a prior RSSI_B reading and a subsequent RSSI_B? reading will indicate whether intermodulation interference is present.

Abstract: Methods and systems for minimizing distortions in an analog data signal include equalizing the analog data signal at a receive end. In an embodiment, the invention adapts equalization parameters to a signal path associated with the analog data signal. Adaptive control logic is implemented with analog and/or digital components. In an embodiment, the invention equalizes a discreet-time analog representation of an analog data signal. In an embodiment, the invention digitally controls equalization parameters. In an embodiment, a resultant equalized analog data signal is digitized. In an example implementation, an analog data signal is sampled, a quality of the samples is measured, and one or more equalization parameters are adjusted with digital controls as needed to minimize distortion of the samples. The equalized samples are then digitized. The present invention is suitable for lower rate analog data signals and multi-gigabit data rate analog signals.

Abstract: A system for transmitting packets over a home network of communication channels, typically coax cable, including a set of nodes, at least one having a packet aggregation functionality in which the node forms an aggregation frame by aggregating one or more packets which have accumulated at the node and transmits the frame. A network coordinator coordinates access of the nodes to the channels. At least one node is operative to inform the coordinator when it has formed an aggregation frame comprising a plurality of packets and to provide the coordinator with comparison information comparing different transmission possibilities for the frame. The coordinator, preferably responsively, determines whether, when, and which of, the aggregated packets can be transmitted.

Abstract: Satellite set-top boxes (STB) are increasingly being designed with multiple tuners, making them capable of receiving more than one program at a time. In addition, satellite STBs are increasingly being designed with multiple inputs, to permit reception of additional channels that will not fit within the conventional satellite intermediate frequency (IF) band (950-2150 MHz). Often, the STB must route these multiple inputs to the multiple tuners with some form of switching function, to allow each tuner to receive all channel bands. Accordingly, the invention includes an RFIC with two RF inputs and three RF outputs, and a crossbar switch that can route any input to any output. The two inputs are amplified by low-noise amplifier stages.

Abstract: A system for transmitting packets over a network of communication channels, the system comprising a set of nodes comprising at least first and second nodes and a network access coordinator operative to coordinate the access of the set of nodes to a synchronous network of channels, wherein, if at least one individual packet has been transmitted from the first node to the second node which did not receive at least one packet, the second node is operative to send a retransmission request to the network access coordinator requesting retransmission of at least one individual packet.

Abstract: A computing device operates over a range of voltages and frequencies and over a range of processor usage levels. The computing device includes at least a variable frequency generator, a variable voltage power supply and voltage supply level and clocking frequency management circuitry. The variable frequency generator is coupled to the processor and delivers a clock signal to the processor. The variable voltage power supply is coupled to the processor and delivers voltage to the processor. The voltage supply level and clocking frequency management circuitry adjust both the voltage provided by the variable voltage power supply and the frequency of the signal provided by the variable frequency generator. The computing device includes a temperature sensor that provides signals indicative of the temperature of the processor and the voltage supply level and clocking frequency management circuitry adjusts the voltage and/or the clocking frequency provided by the variable voltage power supply.