Abstract: An ADSL transceiver chip is provided that includes an analog front-end and a digital signal processor (DSP) integrated on the same substrate. A line driver for the ADSL transceiver can be located on a separate substrate. In embodiments of the invention, the transceiver chip is implemented in a CMOS process. For example, the process could be a low voltage CMOS process. It is highly advantageous to build the analog front-end and the DSP on a single integrated IC because it allows for reduced manufacturing part count, reduced assembly time and cost. Furthermore, the line driver substrate can require a high voltage semiconductor process (e.g. 18 volts peak-to-peak) in some applications, because of the need for adequate voltage to drive the ADSL line. Whereas, the analog front-end and the DSP do not need the such a high-voltage process as required for the by the line driver 102. For example, the analog front-end and DSP can operate with 3.3 v or 5.0 v peak-to-peak.

Abstract: An improved method and apparatus for using common mode feedback to maintain a predetermined DC level for an intermediate frequency output signal. A common mode feedback capacitor-select switch module is operable to use a bandwidth control signal from a radio interface of a wireless device to selectively connect a plurality of common mode feedback capacitors to an operational amplifier, thereby generating a common mode feedback signal as an input to an active mixer conversion gain module. The predetermined combination of common mode feedback capacitors is used in combination with a plurality of bandwidth capacitors to generate an overall capacitance that maintains the bandwidth of the system at a predetermined value.

Abstract: In one embodiment, a portable computerized data communication device in a data communication system may include, for example, a user interface; a computerized system controlling operation of the device; a device housing having a normal closed condition defining an interior space within the device housing, and having an interior electrical connector within the interior space; and the device having an open condition providing access to the interior space while the device housing is in the open condition to enable connection with the interior electrical connector of a peripheral device equipping the device to perform a new function.

Abstract: A system, device and method are disclosed for predicting the opacity of primitives used to produce an image using one or more equations, prior to producing an image. More specifically, the present invention relates to a 3D device adapted to produce an image comprising an opacity estimate predictor adapted to predict opacity of at least one primitive using at least one first equation and further adapted to reject the primitive if the predicted opacity is equal to a minimum value.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: A microprocessor system architecture is disclosed which allows for the selective execution of programmed ROM microcode or, alternatively, RAM microcode if there has been a correction or update made to the ROM microcode originally programmed into the system. Patched or updated RAM microcode is utilized or executed only to the extent of changes to the ROM microcode, otherwise the ROM microcode is executed in its normal fashion. When a patch is received, it is loaded into system RAM along with instructions or other appropriate signals to direct the execution of the patched or updated microcode from RAM instead of the existing ROM microcode. Various methods are presented for selecting the execution of the appropriate microcode depending upon whether there have been changes made to it.

Abstract: A method for providing dynamic adjustment of frame encoding parameters to improve transmission performance for a transmitting frame being transmitted from a transmitting station to a receiving station over a transmission medium on a frame-based communications network, the transmitting frame having a header segment and a payload segment, the header segment being transmitted using a fixed set of encoding parameters, the payload segment being transmitted using a variable set of payload encoding parameters.

Abstract: A method and apparatus are disclosed for using a general purpose input-output (GPIO) interface to test a user input device such as a wireless keyboard or mouse. Operation of key-scan logic can be tested by the GPIO interface by temporarily disconnecting the outputs of the various rows and columns and substituting signals generated by a test algorithm into the input terminals of the key-scan logic. The test signal is processed by the key scan circuitry and a key-scan output signal is generated. This key-scan output signal is then compared to a known reference output signal to determine if the key-scan logic and associated circuitry is operating properly. Other embodiments of the GPIO testing system can be used to test other user devices such as a computer mouse/scrolling device.

Abstract: An integrated receiver with dual channel transport stream decoding and delivery substantially implemented on a single CMOS integrated circuit is described. For multiple channel transfers to hard disk drive storage, a multiplexed IDE host interface is provided with shared pins for data, address, and chip-select lines of the IDE interface so that multiple hard drives may be interfaced using the common pins of the integrated circuit.

Abstract: A printed circuit board includes two differential signal traces, a layer of core material, a layer of filler material, and a ground plane. The filler material is replaced by an air core under the differential signal traces.

Abstract: A cable modem system and method is provided for the transfer and processing of data in accordance with specialized data transfer protocols while utilizing conventional cable modem termination system (CMTS) equipment. A cable modem system in accordance with the invention includes a cable modem that provides for the modification of data packets in accordance with a proprietary protocol and the addressing of the modified data packets to a headend server. The headend server is adapted to reconstruct the data packets for transmission to other local cable modems or to a packet-switched network. In additional embodiments, the CMTS itself rather than a headend server operates to reconstruct the data packets.

Abstract: Certain aspects of changing message filter coefficients dynamically in a packetized network system may comprise selecting a filter for filtering data in a first portion of an incoming data stream. At initiation of a new modification process, a determination may be made as to whether the selected filter is in use and if so, data read by the selected filter may be invalidated or otherwise not utilized for its intended purpose. A selected filter may be marked as being in use prior to being updated, indicating that there is no match for the selected filter. Filter coefficients for the selected filter may be updated while the selected filter is marked as being in use. Upon completion of updating the filter, the selected filter may be marked as not being in use.

Abstract: Systems and methods that expedite connection negotiations. In one embodiment, a method expedites an upper layer protocol (ULP) negotiation between a first node and a second node. The method may include, for example, sending a modified acknowledgement packet from the first node to the second node, the modified acknowledgement packet including information that is used to retrieve parameters agreed upon by the first node and the second node in a previous ULP negotiation between the first node and the second node.

Abstract: A tool for analyzing timing violations reports is presented herein. The tool comprises a script which parses a log file containing any number of timing violation reports from a simulation of a layout design. The tool filters, consolidates, and sorts the timing violations and presents the foregoing in a report of consolidated timing violations. The report of consolidated timing violations can then be analyzed by a verification engineer.

Abstract: A cable modem system and method is provided for supporting data transfer protocols that extend beyond standard protocols used in conventional data over cable systems. A cable modem in accordance with the invention determines, during registration, whether a CMTS with which it communicates is capable of supporting an extended protocol, and if it is, transfers data to the CMTS in accordance with the extended protocol. Additionally, a CMTS in accordance with the invention is notified during registration whether or not a cable modem supports an extended protocol and stores this information. When a request for transmission opportunity is subsequently received from the cable modem, the CMTS accesses the stored information to determine if the cable modem supports the extended protocol. If the cable modem supports the extended protocol, the CMTS processes data received from the cable modem during the transmission opportunity in accordance with that protocol.

Abstract: A method is used that substantially simultaneously trellis encodes data to be modulated onto multiple tones. The embodiments of the present invention comprise the steps of: (a) using a first input operand comprising state bits for a first trellis stage; (b) using a second input operand comprising a plurality of input data bits; and (c) generating an output comprising output data bits and output state bits from a first or later trellis stage.

Abstract: A radio frequency (RF) front-end includes a power amplifier module and a power amplifier control module. The power amplifier module is coupled to amplify an outbound RF signal in accordance with a control signal to produce an amplified outbound RF signal. The power amplifier control module is coupled to generate the control signal based on at least one of forward power of the amplified outbound RF signal and reflected power of the amplified outbound RF signal.

Abstract: A radio frequency integrated circuit (RFIC) includes a silicon substrate, CMOS processing circuitry, and a bipolar power amplifier module. The CMOS processing circuitry is on the silicon substrate. The bipolar power amplifier module is on the silicon substrate and is operable in a 5 GHz frequency band.

Abstract: A receiver includes a plurality of RF receiver modules, a plurality of analog baseband sections, a plurality of analog to digital conversion sections, and a digital baseband processing module. The RF receiver modules convert inbound RF signals into a plurality of inbound analog signals. When the receiver is in a first mode, one of the plurality of analog baseband sections is active to adjust one of the plurality of inbound analog signals to produce an adjusted inbound analog signal; one of the plurality of analog to digital conversion sections converts the adjusted inbound analog signal into an inbound digital signal; and a portion of the digital baseband processing module is active to convert the inbound digital signal into inbound data.

Abstract: Intended for an information security application, particularly in networked information systems, the present invention includes two methods and systems for verifying a current performance of a command by a controller. A first cyclic redundancy check (CRC) for the command is prestored in memory. A second CRC for the command is calculated after instructions of the command have been performed by the controller. The first CRC is compared with the second CRC. Preferably, the controller is reset if the first CRC does not match the second CRC. Also, an address of a first instruction of the command is compared with an address of a second instruction of the command to determine if there may be a discontinuity between the first and the second instructions. It is determined if the first instruction is a valid instruction from/to which an instruction sequence of the command can be redirected.