Abstract: A dual link transmitter constructed according to the present invention employs a single Phase Locked Loop (PLL) to service both a primary link and a secondary link during dual link mode operations. The structure of the dual link transmitter includes both a primary link PLL and a secondary link PLL. The primary link PLL produces a primary link clock and the secondary link PLL produces a secondary link clock. During dual single link operations, the primary link clock is used to service the primary link while the secondary link clock is used to service the secondary link. However, during dual link operations, the primary link clock is used to service both the primary link and the secondary link.

Abstract: A high-speed CMOS transmit/receive antenna switch includes a first transistor, a second transistor and a parasitic compensation network. The first transistor is operably coupled to an antenna, to a transmit path, and to receive a transmit/receive (T/R) control signal. The second transistor is operably coupled to the antenna, the receive path, and to receive the T/R control signal. When the T/R control signal is in a first state, the first transistor is active and the second transistor is inactive such that the transmit path is coupled to the antenna. When the T/R control signal is in a second state, the second transistor is active and the first transistor is inactive such that the receive path is coupled to the antenna. The parasitic compensation network is coupled to compensate for adverse effects of parasitic components of the first and second transistors at operating frequencies of the transmit/receive antenna switch.

Abstract: An analog-to-digital converter (ADC) disposed in a data reception path to convert data from an analog format to a digital format is switched between two or more power modes to conserve power when data is not being received. ADC stays in a lower power-lower precision mode until an inbound data is detected, at which time the ADC switches to a higher power-higher precision mode to convert the data. Once data conversion is completed, the ADC switches back to the lower power-lower precision mode to conserve power.

Abstract: An input power supply voltage level detection circuit and method are presented. The circuit includes a main detector core and a two-inverter buffer block that can include a first inverter and a second inverter. The circuit receives a voltage input signal and outputs a voltage output signal that is substantially equal to either the voltage input signal or ground, depending on whether the voltage input signal has reached a threshold voltage. The threshold voltage is defined by component characteristics of the main detector core and the two-inverter buffer block. The circuit can receive a hysteresis input signal, tied to the voltage input signal or the ground, that allows the threshold voltage to have a first threshold value when the voltage input signal increases and a second threshold value when the voltage input signal decreases. A power down input signal can also be received that allows the circuit to be powered down.

Abstract: A method and apparatus for trimming of a local oscillation within a radio frequency integrated circuit (RFIC) includes processing that begins when an RFIC receives a radio frequency (RF) signal having a known frequency. The processing then continues when the RFIC mixes the RF signal with a receiver local oscillation to produce a low intermediate frequency (IF) signal, which may have a carrier frequency of zero (i.e., a baseband signal) or up to a few mega Hertz). The processing then continues when the RFIC demodulates the low IF signal to produce demodulated data. The processing then continues as the RFIC determines a DC offset from the demodulated data, where the DC offset is reflective of the difference between the known frequency and the frequency of the receiver local oscillation. The processing then continues as the RFIC adjusts the receiver local oscillation to reduce the DC offset when the DC offset compares unfavorably with an allowable offset threshold.

Abstract: A transmitter includes a first amplifier to amplify an in-phase oscillator signal to produce an in-phase mixing signal and a second amplifier to amplify a quadrature-phase oscillator signal to produce a quadrature-phase mixing signal. A first mixer mixes the in-phase mixing signal with a first information signal to produce a first output signal. A second mixer mixes the quadrature-phase mixing signal with a second information signal to produce a second output signal. The first output signal and an inverted second output signal are summed to produce a transmitter output signal that includes an image signal caused by a phase imbalance between the in-phase and quadrature-phase mixing signals. An image monitor monitors the image signal and reduces or eliminates the phase imbalance by independently adjusting a phase of the in-phase mixing signal and/or a phase of the quadrature-phase mixing signal. Consequently, a power of the image signal is reduced or eliminated.

Abstract: The present invention is directed to systems and method for attenuating intermodulation interference. In particular, methods and systems to attenuate intermodulation interference contained within an aggregate signal having a transmitted signal that was transmitted over a communications channel having channel effects that produce the intermodulation interference are provided. The communications channel may be a cable television distribution network and the signal may be a cable television signal. A method is provided to predict when intermodulation interference will be large, so that actions within a receiver can be taken to reduce the impact of the interference and improve overall receiver performance.

Abstract: A power amplifier circuit including a first transistor, a second transistor, and a power control circuit. The first transistor includes a first input and a first output. The second transistor includes a second input coupled in series with the first output of the first transistor. The input circuit is coupled to the second input of the second transistor. The control circuit includes a time delay circuit and a variable source.

Abstract: A multi-protocol wireless communication baseband transceiver includes a baseband transmit processing module and a baseband receive processing module. The baseband transmit processing module includes an encoding module, an interleaving module, a plurality of symbol mapping modules, a plurality of domain conversion modules, a plurality of cyclic prefix modules, a plurality of compensation modules, and a control module that is operably coupled to produce preamble set up information and payload set up information based on a mode of a plurality of protocol modes.

Abstract: Self-generated automated tests can use a pseudo-random number generator to select one or more arguments that are passed to programs and scripts. The random arguments are driven by a configuration file where the limits for the parameters are defined. Multidimensional functions with multidimensional parameters can be tested. Test duration can be limited by time, number of iterations, or by any of the multidimensional functions or parameters. A pseudo-random seed for each test is recorded so that a test case can be reproduced if a failure is detected or otherwise.

Abstract: A method is described for correcting sampling frequency offset (SFO) of a data packet in a communications system where carrier frequency (fc) and sampling frequency (fs) are driven by a common clock source. The method comprises, for each lth symbol in the data packet, estimating carrier frequency offset (CFO) in a received data packet. From the CFO estimate, an SFO estimate is derived, wherein the SFO is approximately equal to fs multiplied by said CFO estimate, and divided by fc. An SFO phase correction is generated according to the SFO estimate for each kth tone in a data stream. The SFO phase correction is then applied to each received data stream.

Abstract: Provided a method of reducing impedance variations in an electrical circuit structured and arranged for placement on an integrated circuit (IC) substrate. The method includes forming sets of parallel connected resistors, each set corresponding to one of the impedance devices on the IC. Each set also includes two or more parallel resistor paths, each resistor path including two or more cascaded resistors and has a total impedance value substantially equal to the predetermined impedance value of its corresponding impedance device. Finally, the method includes configuring the sets of parallel resistor paths to form an interdigital structure across the substrate when the electrical circuit is placed on the IC.

Abstract: A single chip radio transceiver includes circuitry that enables received RF signals to be down-converted to baseband frequencies and baseband signals to be up-converted to RF signals prior to transmission without requiring conversion to an intermediate frequency. The circuitry includes a low noise amplifier, automatic frequency control circuitry for aligning the LO frequency with the frequency of the received RF signals, received signal strength indicators for adjusting frontal and rear amplification stages accordingly, and, finally, filtering circuitry to filter high and low frequency interfering signals, including DC offset.

Abstract: Multi-carrier modulation fiber optic systems constructed using a series of electrical carriers, modulating the data on the electrical carriers and combining the carriers to form a wideband signal. The wideband signal can then be intensity modulated on a laser and coupled to a fiber optic channel. A receiver may then receive the laser signal from the fiber optic channel and convert it into an electrical signal. Multi-carrier modulation may be applied to existing fiber channels, which may be of lower quality. Existing fiber channels may have characteristics which prevent or restrict the transmission of data using intensity modulation at certain frequencies. An adaptive multi-carrier modulation transmitter may characterize an existing fiber optic channel and ascertain the overall characteristics of the channel. The transmitter and receiver can then be configured to use various bandwidths and various modulations in order to match the transfer characteristic of the fiber channel.

Abstract: A scaled input current is produced that substantially matches the full scale input of a CT??ADC that substantially cancels an offset bias current component of the input current. A variable bias resistance value is coupled between the integrator input and one of a supply voltage and a circuit common. The method further includes integrating the input current to produce an integrated signal representing a time averaged value of the input current to substantially remove noise from a frequency band of interest. The integrated signal is produced to a quantizer to produce a feedback current that substantially cancels a quantization noise component in the digital representation of the scaled analog signal by coupling the digital representation of the scaled analog signal to a programmable digital switch wherein the programmable digital switch either sinks current from or sources current to the integrator input.

Abstract: Disclosed herein are debugging tool(s) for profiling the frequency of execution of certain instructions in a host operation. The debugging tool causes interrupts to occur at random time intervals and records the address of the program counter at each interrupt. A profile is developed that indicates the frequency of execution of certain instructions after a statistically significant number of interrupts.

Abstract: A method and apparatus for parallel decoding of turbo encoded data. The method includes multiple Soft In Soft Out (SISO) modules arranged in parallel such that each module supplies an input to one SISO and takes an input from another SISO data encoded for multiple parallel SISOs is received by a receiver and decoded in the abovementioned parallel configuration.

Abstract: LDPC (Low Density Parity Check) coded modulation symbol decoding. Symbol decoding is supported by appropriately modifying an LDPC tripartite graph to eliminate the bit nodes thereby generating an LDPC bipartite graph (such that symbol nodes are appropriately mapped directly to check nodes thereby obviating the bit nodes). The edges that communicatively couple the symbol nodes to the check nodes are labeled appropriately to support symbol decoding of the LDPC coded modulation signal. The iterative decoding processing may involve updating the check nodes as well as estimating the symbol sequence and updating the symbol nodes. In some embodiments, an alternative hybrid decoding approach may be performed such that a combination of bit level and symbol level decoding is performed. This LDPC symbol decoding out-performs bit decoding only. In addition, it provides comparable or better performance of bit decoding involving iterative updating of the associated metrics.

Abstract: A method and apparatus for dynamic frequency selection in a wireless communication system or network includes processing that begins when an access point determines interference on a wireless channel that is being used by the access point. When the interference exceeds an interference threshold, the access point provides a request packet to affiliated stations being serviced by the access point for channel spectrum information. The processing continues as the affiliated stations generate the channel spectrum information regarding each of the wireless channels in the wireless communication network. The processing proceeds then as the affiliated stations provide the channel spectrum information to the access point via the current wireless channel. The access point interprets the channel spectrum information to determine a desired wireless channel of the plurality of wireless channels within the wireless communication network.

Abstract: An impulse-reducing module (200) reduces random noise in video pixels by providing an impulse detector (244) and an impulse reducer, such as a median filter (250). The impulse detector (244) generates filter control signals in response to detection of impulses, and the median filter (250) generates filtered pixel values in response to the filter control signals. The control signals set the median filter to a plurality of filter operating modes.