Abstract: Interchangeable integrated circuit building blocks include functionally equivalent integrated circuit building blocks, having similar footprints, and having one or more dissimilar features or operational characteristics. The functionally equivalent integrated circuit building blocks are interchangeable in a design layout without having to re-place and re-route. The functionally equivalent integrated circuit building blocks are optionally interchangeable on a building block by building block basis. One or more detection features are optionally included in one or more of the interchangeable integrated circuit building blocks. The detection features facilitate detection of the interchangeable integrated circuit building blocks. Area, space, and/or width design rule checks are optionally focused at junctions of detected integrated circuit building blocks.

Abstract: Provided is a system and method for converting digital data audio data audio data that has a predetermined input sample rate, into an analog data signal. A system includes a digital to analog converter (DAC) including a digital processing portion configured to receive as an input the digital audio data and timing information, the timing information being representative of a time base of the input sample rate. The digital processing portion is similarly configured to digitally process the digital audio data and the timing information to produce serialized output data. The DAC also includes an analog processing portion configured to convert serialized data to an analog format. The digital processing portion operates in accordance with at least one clock having a corresponding clock rate wherein the corresponding clock rate is unrelated to the input sample rate.

Abstract: Satellite communications are carried out using the Data Over Cable Interface Specification (DOCSIS). Satellite modems are notified of upstream channel congestion by inserting a congestion notification message in a medium access protocol (MAP) message for the upstream channel. Specifically, the congestion notification message is inserted in an unused field of the MAP message, such as the explicit congestion notification (ECN) field. The MAP message can also carry other characteristics of the upstream channel, including priority threshold, multicast access burst availability, and available bandwidth.

Abstract: A switch regulator includes an inductor, a reference transistor, a first switching transistor, and a second switching transistor. The first switching transistor includes a gate electrode, a first main electrode (e.g., a source or a drain), and a second main electrode (e.g., a source or a drain). The first switching transistor is coupled in series with the inductor when it is turned on by a clock. The first main electrode (e.g., the source or the drain) of the switching transistor is connected to a ground or a fixed voltage power supply. A reference voltage may then be generated by flowing a current through the reference transistor. As such, the switch regulator contains an over-current detector that is flexible in size of current to be detected while consuming a relatively small amount of space and having substantially low cost on the overall efficiency of the switch regulator.

Abstract: An imaging device includes a plurality of photo-diodes that operate as optical pixels arranged in a plurality of columns on a single CMOS substrate. The outputs of the multiple pixel sensors, or photo-diodes, are examined to determine if a one pixel, or a region of pixels are in saturation. If so, then the pixel gain is adjusted to correct or compensate for the image distortion in the region. For example, the gain of the charging amplifier or operational amplifier can be adjusted to correct for saturation. This can be done in real-time since hardware is being tuned for the correction instead of software.

Abstract: A method for avoiding out-of-ordering of frames in a network, wherein the method includes the steps of providing at least one first type of queue in a network switch, providing at least one second type of queue in a network switch, and receiving an incoming packet. The method further includes first storing the incoming packet in the at least one first type of queue if the packet is from a first source, second storing the incoming packet in the at least one second type of queue if the packet is from a second source, and sending the incoming packet to a desired destination. Additionally, a method for avoiding out-of-ordering of frames in a network including the steps of receiving an incoming packet at a network switch, determining if the incoming packet is from a high speed source, first storing the incoming packet in a first type of queue, if the incoming packet is from said high speed source, and second storing the incoming packet in a second type of queue, if the incoming packet is from a lower speed source.

Abstract: The invention enables an increase in linearity of a power amplifier while reducing current consumption by supplying a bias current to the power amplifier in a Class AB mode.

Abstract: A communication network having at least one access point supports wireless communication among a plurality of wireless roaming devices via a first and a second wireless channel. The access point comprises a first and a second transceiver. The first and second transceivers operate on the first and second wireless channels, respectively. Each of the plurality of wireless roaming devices are capable of communicating on the first and second wireless channel. In one embodiment, the first wireless channel is used to exchange data, while the second channel is used to manage such exchanges as well as access to the first channel. In an alternate embodiment, both channels are used to support communication flow, however the first channel supports a protocol that is more deterministic than that of the second channel. Allocation of ones of the plurality of wireless roaming devices from one channel to the next may occur per direction from the access point.

Abstract: A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input signal terminal, where the phase locked loop circuit is capable of generating a plurality of output signals that are frequency locked to the reference signal and having a plurality of different phases, a phase rotator coupled to the phase locked loop circuit, where the phase rotator generates an even greater plurality of phases.

Abstract: A communication network having at least one access point supports wireless communication among a plurality of wireless roaming devices via a first and a second wireless channel. The access point comprises a first and a second transceiver. The first and second transceivers operate on the first and second wireless channels, respectively. Each of the plurality of wireless roaming devices are capable of communicating on the first and second wireless channel. In one embodiment, the first wireless channel is used to exchange data, while the second channel is used to manage such exchanges as well as access to the first channel. In an alternate embodiment, both channels are used to support communication flow, however the first channel supports a protocol that is more deterministic than that of the second channel. Allocation of ones of the plurality of wireless roaming devices from one channel to the next may occur per direction from the access point.

Abstract: A system and method are used to maintain a variance in feedback factors of an amplifier between the first and second phases either below a threshold value or within a specified range. The system includes the amplifier and first through third capacitances. The amplifier is coupled between an input node and an output node that operates during first and second phases of operation. The first capacitance is coupled across the amplifier and between the input node and the output node during the first and second phases of operation. The second capacitance is coupled to the input node during the first phase of operation. The third capacitance is coupled to one of the input and output nodes during one or both of the first and second phases of operation.

Abstract: A network interface is presented that receives packet data from a shared medium and accomplishes the signal processing required to convert the data packet to host computer formatted data separately from receiving the data packet. The network interface receives the data packet, converts the analog signal to a digitized signal, and stores the resulting sample packet in a storage queue. An off-line processor, which may be the host computer itself, performs the signal processing required to interpret the sample packet. In transmission, the off-line process converts host-formatted data to a digitized version of a transmission data packet and stores that in a transmission queue. A transmitter converts the transmission data packet format and transmits the data to the shared medium.

Abstract: A method and system are provided for removing discontinuities associated with synthesizing a corrupted frame output from a decoder including one or more predictive filters. The corrupted frame is representative of one segment of a decoded signal. The method comprises copying a first number of stored samples of the decoded signal in accordance with a time lag and a scaling factor, and calculating a first number of ringing samples output from at least one of the filters.

Abstract: Methods and apparatus are provided for implementing a cryptography engine for cryptography processing. A variety of techniques are described. A cryptography engine such as a DES engine can be decoupled from surrounding logic by using asynchronous buffers. Bit-sliced design can be implemented by moving expansion and permutation logic out of the timing critical data path. An XOR function can be decomposed into functions that can be implemented more efficiently. A two-level multiplexer can be used to preserve a clock cycle during cryptography processing. Key scheduling can be pipelined to allow efficient round key generation.

Abstract: A system and method are used to accelerate settling or steady state of an amplifier in an amplifier system. This is used to ensure the amplifier reaches steady-state within a specified time period from stand-by or another state without using more current than is needed for steady-state. A comparator in a common-mode feedback system compares a desired amplifier output signal to one or more nodes of the amplifier. A result of the comparison is compared to a threshold value using a comparator in a settling acceleration system. If the result crosses the threshold, a controller turns on a driver in the settling acceleration system. The driver pulls on one or more nodes of the amplifier, which, along with a driver in the amplifier system pulling on the node, quickly brings the amplifier to settling or steady state.

Abstract: A packet-based, hierarchical communication system, arranged in a spanning tree configuration, is described in which wired and wireless communication networks exhibiting substantially different characteristics are employed in an overall scheme to link portable or mobile computing devices. The network accommodates real time voice transmission both through dedicated, scheduled bandwidth and through a packet-based routing within the confines and constraints of a data network. Conversion and call processing circuitry is also disclosed which enables access devices and personal computers to adapt voice information between analog voice stream and digital voice packet formats as proves necessary. Routing pathways include wireless spanning tree networks, wide area networks, telephone switching networks, internet, etc., in a manner virtually transparent to the user.

Abstract: Aspects of the invention provide a fast one level zero-current-state XOR gate. An embodiment of the invention provides a first pair of differentially configured transistors and a level shifting resistor coupled to the first pair of differentially configured transistors. The one level zero-current-state XOR gate may also include a second pair of differentially configured transistors. A core of the XOR gate may be coupled to outputs of the first and the second pairs of differentially configured transistors.

Abstract: A transport protocol receiver for receiving a packet from a network, the packet having a header, payload, and connection context. The receiver includes an analysis engine, coupled to receive the packet from the network and adapted to parse and validate the header, locate the connection context, and generate a classification of the header. The receiver further includes a context processing engine, coupled to the analysis engine, and adapted to evaluate and update the connection context, responsive to the classification; and a data dispatch engine, coupled to the analysis engine and the context processing engine, and adapted to convey the payload to a destination, responsive to the connection context, such that the analysis engine, the context processing engine, and the data dispatch engine operate substantially asynchronously.

Abstract: A digital-to-analog converter (DAC) disposed in a data transmission path to convert data from a digital format to an analog format to be transmitted is powered down during a receive mode of operation for a wireless communication device. Likewise, an analog-to-digital converter (ADC) disposed in a data reception path to convert received data from an analog format to a digital format is powered down during a transmit mode of operation.

Abstract: An apparatus and method for enabling functionality of a component, wherein the apparatus includes a random number generating module for generating a random number, and a hash function module in communication with the random number generating module. A host is provided in communication with the random number generating module, and at least one memory in communication with the host is included. An encryption module in communication with the at least one memory is provided, and a comparing device in communication with the encryption module and the hash function module is included. The comparing device of the apparatus compares a first bit string to a second bit string to generate a function enable output for the component.