Abstract: A charge pump includes a resistor divider connected between an output voltage node and ground and a comparator inputting a reference voltage at one input, and a divided voltage from the resistor divider at another input. A digital control circuit is enabled by the comparator. A first transistor and a second transistor are in series between an input voltage node and the ground, both transistors controlled by the digital control circuit. A pump capacitor is connected between to the output voltage node and between the first and second transistor, and being charged by turning the first and second transistors on and off. A first diode is between the pump capacitor and the input voltage node. A second diode between the pump capacitor and the output voltage node. A reservoir capacitor between the output voltage node and ground. The digital control circuit comprises a first shift register.

Abstract: A receiver includes a filter for filtering a received signal to produce a filtered signal. A converter converts the filtered signal to a baseband signal that is substantially free of an initial frequency offset and inter-symbol interference (ISI), responsive to a frequency-offset estimate and a restorative signal that compensates for the ISI. A detector detects symbols in the baseband signal to produce a decision signal. A restorative signal generator generates, from the decision signal, the restorative signal responsive to the frequency-offset estimate, such that the restorative signal compensates for the ISI.

Abstract: The invention relates to generating a test suite of instructions for testing the operation of a processor. A fuzzy finite state machine with a plurality of states 2 and transitions 4 determined by weights W1, W2 . . . W10 is used to generate a sequence of instructions. The weights determine the next state as well as an instruction and operands for each state. The weights may be adapted based on the generated sequence and further sequences are generated.

Abstract: A system for detecting connector compatibility with a time domain reflectometry (TDR) circuit on a peripheral device. A cable connects the peripheral device and a second peripheral device. A first connector is for mating to a second connector on the second peripheral device. The time domain reflectometry can be used to detect electrical compatibility of the first and second connectors. The first connector can be an RJ11 connector. The second connector can be an RJ45 connector. The first connector can be a plug, and the second connector can be a socket. The number of pins of the first and second connectors can be different. The first connector can be a telco connector, and the second connector can be an Ethernet connector. The TDR circuit can be part of the peripheral device diagnostics.

Abstract: An operational amplifier includes a first stage with a first differential transistor pair inputting a differential input signal at their gates, a first tail current source transistor connected to sources of the first differential transistor pair, and a load transistor pair connected in series with the drain of first differential transistor pair. An input stage includes a second differential transistor pair connected to respective drains of the first differential transistor pair at their gates, and a second tail current transistor connected to sources of the differential transistor pair. An output stage outputs a signal corresponding to the differential input signal.

Abstract: A memory access system is described which generates two memory addresses from a single memory access instruction which identifies a register holding at least two packed objects. In the preferred embodiment, the contents of a base register is combined respectively with each of two or more packed objects in an offset register.

Abstract: In a communications system (such as cable modem communications), dynamic payload header suppression (DPHS) is applied to a data stream to reduce header overhead. DPHS allows the suppression of static fields as well as fields that change in a predictable manner (i.e., predictably dynamic fields). To suppress predictably dynamic fields, delta encoding is utilized to enable a cable modem to replace a dynamic field with information indicating how the field is different from the same field in a previous packet in the data stream. DPHS constructs a suppression mask by using a special packet called a “learn” packet. The “learn” packet is a copy of the original packet with extra bytes that guide the suppression process. It indicates that both the sending and receiving entities are to take a full copy of a packet header, which is then used as a reference to reconstruct the suppressed fields.

Abstract: A technique for performing frame erasure concealment (FEC) in a speech decoder. One or more non-erased frames of a speech signal are decoded in a block-independent manner. When an erased frame is detected, a short-term predictive filter and a long-term predictive filter are derived based on previously-decoded portions of the speech signal. A periodic waveform component is generated using the short-term predictive filter and the long-term predictive filter. A random waveform component is generated using the short-term predictive filter. A replacement frame is generated for the erased frame. The replacement frame may be generated based on the periodic waveform component, the random waveform component, or a mixture of both.

Abstract: RF communications received by a wireless terminal from a servicing base station are used to determine the downlink quality report and implement link adaptation decisions. This involves first implementing an initial transmission scheme between the servicing base station and the wireless terminal. Next, a current downlink quality report corresponding to the initial transmission scheme is generated by the wireless terminal and received at the servicing base station. This downlink quality report is based in whole or in part on a bit-error probability (BEP). The current downlink quality report that corresponds to the initial transmission scheme is then compared to link adaptation thresholds.

Abstract: A method and system to determine when a wireless terminal has been paged by a servicing base station. An encoded paging burst is received on a paging channel and then decoded to produce a decoded paging burst. The decoded paging burst is processed to determine if it is a null page. When the encoded paging burst is a null page, it is processed to produce a null page pattern. The wireless terminal may then enter a sleep mode or reduced functionality mode for a predetermined period of time. The wireless terminal awakes from the sleep mode to receive additional encoded paging bursts. Processing the additional encoded paging bursts produces a processed encoded paging burst, which is compared to the null page pattern. When compared favorably, the encoded paging burst is considered a null page, allowing the wireless terminal to re-enter the sleep mode without fully decoding the paging burst.

Abstract: A method and apparatus are disclosed for enhancing the pipeline instruction transfer and execution performance of a computer architecture by reducing instruction stalls due to branch and jump instructions. Trace cache within a computer architecture is used to receive computer instructions at a first rate and to store the computer instructions as traces of instructions. An instruction execution pipeline is also provided to receive, decode, and execute the computer instructions at a second rate that is less than the first rate. A mux is also provided between the trace cache and the instruction execution pipeline to select a next instruction to be loaded into the instruction execution pipeline from the trace cache based, in part, on a branch result fed back to the mux from the instruction execution pipeline.

Abstract: A method of preventing Hot Carrier Injection in input/output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the external voltages that those circuits can tolerate. By placing input/output devices, in series, external voltages can be divided between the devices thereby reducing junction voltages seen by internal devices. A circuit for preventing Hot Carrier Injection in these input/output devices comprises comparing an input voltage to a reference voltage, and if conditions that would produce Hot Carrier Injection are present (e.g. when input voltage is greater than reference voltage), slowing the turn-on of one of the series connected input/output devices, thereby reducing the voltage from the drain-to-source of another series connected input/output device.

Abstract: A direct conversion satellite tuner is fully integrated on a common substrate. The integrated tuner receives an RF signal having a plurality of channels and down-converts a selected channel directly to baseband for further processing. The integrated tuner includes on-chip local oscillator generation, tunable baseband filters, and DC Offset cancellation. The integrated tuner can be implemented in a completely differential I/Q configuration for improved electrical performance. The entire direct conversion satellite tuner can be fabricated on a single semiconductor substrate using standard CMOS processing, with minimal off-chip components. The tuner configuration described herein is not limited to processing TV signals, and can be utilized to down-convert other RF signals to an IF frequency or baseband.

Abstract: Embodiments of the present invention perform logical operations utilizing a symmetric logic circuit comprising two logic units. In a symmetric logic circuit, the circuit configuration used to process a first logic input in the first logic unit is the same as the circuit configuration used to process a second logic input in the second logic unit, and the circuit configuration used to process the second logic input in the first logic unit is the same as the circuit configuration used to process the first logic input in the second logic unit. The present invention may be used for logic circuits that perform a variety of logical operations, such as XOR, AND, NAND, OR, or NOR.

Abstract: A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the external voltages that those circuits can handle. By placing input and output devices, in series, external voltages can be divided between the devices thereby reducing junction voltages seen by internal devices. By using external voltages as part of a biasing scheme for integrated circuit devices, stress created by the differential between external voltages and internal voltages can be minimized. Additionally device wells can be biased so that they are at a potential that is dependant on the external voltages seen by the low voltage integrated circuit.

Abstract: In association with a circuit for adding binary numbers, it is often useful to increment the sum by a value of 1, for example on a conditional basis. Each of the combined adder and incrementer circuits embodying the invention also provides an output indicating whether a CarryOut signal resulted from the incrementing operation, or whether the CarryOut signal resulted from the addition. The preferred embodiments utilize prefix-type adder circuits using a single carry chain. Alternate embodiments generate a CarryOut signal as a function of the incrementing operation, using either generate and propagate signals or from generate and kill signals from the carry chain.

Abstract: Iterative data-aided carrier CFO estimation for CDMA systems. Any communication receiver may be adapted to perform the iterative data-aided carrier CFO estimation. The iterative data-aided carrier CFO estimation is performed using a high accuracy method. The operation may be described as follows: a received signal is despread and buffered. Using the received preamble sequence, an initial estimate of the CFO is obtained. This estimate is used to correct the whole despread data. The corrected data using the initial CFO estimate is sliced. Each despread data symbol is divided by the corresponding sliced data decision. The obtained sequence is then averaged across different codes to obtain a less noisy sequence, which is then used to estimate the CFO again. The procedure can be repeated (iterated) to obtain a more accurate carrier frequency offset estimate; the number of times in which the procedure is repeated may be programmable or predetermined.

Abstract: Quadrature receiver sampling architecture. A signal ADC performs analog to digital conversion for both I and Q streams. An analog MUX selects the appropriate I and the Q baseband analog input streams for input to the ADC at the appropriate time. A digital filter may also be employed to compensate for any introduced delay between the samples of the I and Q channel when seeking to recover the symbols that have been transmitted to a communication receiver that employs this quadrature receiver architecture and/or signal processing. In one embodiment, if an ADC is clocked at a rate of substantially twice the sample rate of the I and Q channels, there will be a one-half sample clock delay between the digital I and digital Q data at the output of the ADC. This delay is then removed before the demodulator processes the input signals to recover the transmitted symbols.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: A method of handling data packets in a series of network switches includes receiving an incoming data packet at a data port of a first switch of the series of network switches. A module id bitmap of the incoming data packet is resolved and a bit corresponding to the first switch of the module id bitmap is examined to determine if the bit is set. A destination address of the incoming data packet is resolved when the corresponding bit is set and the incoming data packet is forwarded or dropped based on the destination address. When the corresponding bit is not set, the incoming data packet is forwarded to a next switch of the series of network switches. A network switch configured to allow for cascading of data packets is also disclosed.