Abstract: The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to from the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.

Abstract: An apparatus for scaling a load device with frequency in a phase interpolator can include an analog loop and a digital loop. The load device of the phase interpolator can include a transistor and a plurality of resistors selectively configured in parallel with the transistor. The analog loop controls a resistance of the transistor based on a voltage applied to a control terminal of the transistor. For instance, the analog loop can tune the resistance of a PMOS device by adjusting a voltage applied to the PMOS device's gate terminal. In addition, the analog loop can include a comparator to compare a voltage across the transistor to a reference voltage such that an optimal voltage is maintained for an output swing of the phase interpolator. The analog loop can also include a low pass filter coupled to an output of the comparator to define frequency stability and loop bandwidth of the analog loop.

Abstract: A wireless access point and multiple wireless terminals exchange utilization, status, mobility and reception characteristics. Each wireless terminal generates reception characteristics based on transmissions received from the wireless access point and from other devices in the network. In one operating mode, the characteristics gathered by the wireless devices are forwarded to the wireless access point, and, based on all received characteristics, the wireless access point selects its own transmission power for different types of the transmission. In another mode, all characteristics are exchanged between every wireless terminal and the access point so that each can independently or cooperatively make transmission power control decisions. In a further mode, the wireless access point adjusts protocol parameters based on an assessment of the characteristics received from the client devices.

Abstract: A multi-band receiver includes a first receiver coupled to receive a first desired signal component of an RF signal over a first range of frequencies and generate a first received signal. A second receiver receives a second desired signal component of the RF signal over a second range of frequencies and generates a second received signal. The second receiver includes a harmonic cancellation module that attenuates a harmonic of the first desired signal component that falls within the second range of frequencies.

Abstract: A receiver includes an antenna array that generates a plurality of received signals from at least a first remote transmitter and a second remote transmitter. Aa plurality of receiver sections process the plurality of received signals to generate a plurality of down-converted signals. A receiver processing module generates a first plurality of reception matrices corresponding to the first remote transmitter based on the plurality of down-converted signals, generates a first reception statistic from a sum based on the first plurality of reception matrices, and generates an association decision corresponding to one of: the first remote transmitter and the second remote transmitter, based on the first reception statistic.

Abstract: A method for decoding bi-phase encoded data begins by interpreting a first bit boundary of a bit of the bi-phase encoded data to produce a first boundary value. The method continues by interpreting a second bit boundary of the bit of the bi-phase encoded data to produce a second boundary value. The method continues by comparing the first boundary value to the second boundary value to produce a decoded bit.

Abstract: An ESD protection system providing extra headroom at an integrated circuit (IC) terminal pad. The system includes an ESD protection circuit having one or more first diodes coupled in series between the supply voltage and terminal pad, and a second diode coupled to ground. One or more third diodes are coupled in series between the terminal pad and second diode, and are configured to permit a voltage on the interconnection nodes between the one or more third diodes and second diode different from ground. The one or more third diodes include an n+ on an area of P-substrate. A deep N-well separates the area of P-substrate from a common area of P-substrate, which is coupled to ground. The allowable signal swing at the terminal pad is increased to greater than supply voltage plus 1.4 V. The ESD protection circuit is useful for, among other things, relatively low supply voltage ICs.

Abstract: A voice, data and RF integrated circuit includes a processing module that generates at least one control signal that indicates a receive calibration mode. An RF transmitter generates a transmit signal that includes a first calibration signal when the at least one control signal indicates the receive calibration mode. An RF receiver receives a received signal that includes the first calibration signal and generates at least one receiver equalization parameter for equalizing the RF receiver in response to receiver feedback signals, when the at least one control signal indicates the receive calibration mode.

Abstract: According to one exemplary embodiment, a power supply rejection bias circuit includes a first amplifier coupled to a second amplifier, where the first amplifier receives a reference voltage, and a feedback voltage of the bias circuit. The bias circuit further includes an output transistor driven by the output of the second amplifier, where the output transistor provides the output of the bias circuit and the feedback voltage. The bias circuit further includes a feedback resistor coupled between an input and an output of the second amplifier. According to this embodiment, the output of the second amplifier forms a non-dominant pole of the bias circuit and the output of the bias circuit forms a dominant pole of the bias circuit, thereby increasing power supply rejection of the bias circuit.

Abstract: In a wireless communication system, a method and system for implementing the A5/3 encryption algorithm for GSM and EDGE compliant handsets are provided. Input variables may be initialized in a keystream generator and an intermediate value may be generated with a cipher key parameter and a key modifier. A number of processing blocks of output bits may be determined based on a number of bits in an output keystream. The processing blocks of output bits may be generated utilizing a KASUMI operation and may be based on an immediately previous processing block of output bits, the intermediate value, and an indication of the processing block of output bits being processed. The processing blocks of output bits may be generated after an indication that an immediately previous processing block of output bits is available and may be grouped into two final blocks of output bits in the output keystream.

Abstract: Equalization is provided in a high speed communication receiver that includes in various aspects an automatic gain control input stage, a decision feedback equalizer, a clock and data recovery circuit and equalization control circuits. The automatic gain control stage may include a continuous time filter with an adjustable bandwidth. A threshold adjust signal may be applied to the output of the automatic gain control stage. The equalization control circuits may be implemented in the digital domain and operate at a lower clock speed than the data path.

Abstract: A Radio Frequency (RF) receiver includes a RF front end and a baseband processing module coupled to the RF front end that is operable to determine equalizer coefficients for a composite signal that includes a first information signal and a second information signal. First and second information signal channel estimates and channel powers based upon training symbols are determined. A composite signal power is determined. A noise variance of the composite signal is determined based upon the first information signal channel power, the second information signal channel power, and the composite signal power. A plurality of equalizer coefficients are determined based upon the first information signal channel estimate, the second information signal channel estimate, and the noise variance of the composite signal.

Abstract: A method and apparatus to counter effects of an offset voltage by calibrating an analog-to-digital converter (ADC). A digital calibration loop minimizes the effects of offset voltage to improve ADC accuracy as well as provide a low-power, submicron-scale ADC. A calibration circuit senses an ADC output and adjusts a variable calibration voltage to counter the effects of the offset voltage. Reduction of the offset voltage effects increases the ADC accuracy.

Abstract: A loudness enhancement system and method is described that increases the loudness of an audio signal being played back by an audio device that places limits on the dynamic range of the audio signal. In an embodiment, the loudness enhancement system and method compresses the audio signal to an adaptively-determined compression limit that is greater than or equal to a maximum desired output level and then applies an adaptively-determined degree of soft clipping to the compressed audio signal. The compression limit and degree of soft clipping may be determined based on an overload measure that is calculated for successive portions of the audio signal. The loudness enhancement system and method advantageously operates in a manner that generates less distortion than the method of simply over-driving the audio signal such that hard-clipping occurs.

Abstract: A video processing system receives a plurality of video inputs and specifically tailors them to meet the audio/video format requirements of a plurality of recipient video devices. The video processing system may be incorporated into a set top box, personal video recorder, video player, television, or video equipment. The video processing system in the set top box allows multiple users to receive video programs or television broadcasts meeting the audio/video format requirements of the recipient devices of the users. The video processing system allows user to define the audio/video formats of the recipient devices. Alternatively, the video processing system queries the recipient devices and obtains the audio/video format requirements of the video devices. The video processing system delivers multiple audio/video outputs, reformatted from a plurality of audio/video sources on the basis of user input, wirelessly in the operational region or by a wired means to a number of video devices.

Abstract: Systems and methods that process and protect content are provided. In one example, a system may include, for example, a first device coupled to a second device. The first device may include, for example, an integrated circuit that may include a content processing system and a security system. The security system may include, for example, a digital rights manager. The first device and the second device may be part of a network. The network receives content and control information via the first device. The content processing system processes incoming content based upon at least the control information. The integrated circuit protects the content before placing the content on the network.

Abstract: Various example embodiments are disclosed. According to an example embodiment, a method may include receiving a token count units instruction, periodically increasing or decreasing a token count based at least in part on a refresh rate, and in response to receiving a packet, decreasing or increasing the token count based at least in part on a size of the packet and the instruction.

Abstract: A filter settings generation operation includes sampling a communication channel to produce a sampled signal. The sampled signal is spectrally characterized across a frequency band of interest to produce a spectral characterization of the sampled signal. This spectral characterization may not include a signal of interest. The spectral characterization is then modified to produce a modified spectral characterization. Filter settings are then generated based upon the modified spectral characterization. Finally, the communication channel is filtered using the filter settings when the signal of interest is present on the communication channel. In modifying the spectral characterization, pluralities of spectral characteristics of the spectral characterization are independently modified to produce the modified spectral characterization. Modifications to the spectral characterization may be performed in the frequency domain and/or the time domain.

Abstract: A method for supporting communication between a source internet protocol phone and a destination internet protocol phone is provided. The source internet protocol phone communicates via a Network Address Translator (“NAT”) gateway. The method includes receiving a packet from the source phone at the NAT. The packet is for communication with the destination phone. The method further includes querying whether the destination phone is located in the subnetwork serviced by the NAT gateway. If the destination phone is not located in the subnetwork serviced by the NAT gateway, then the method includes sending the packet upstream to the destination phone via the Internet. If the destination phone is located in the subnetwork serviced by the NAT gateway, then the method includes directing the packet to the destination phone.

Abstract: A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Solomon encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed.