Abstract: A high output power radio frequency integrated circuit includes an up conversion module, a plurality of drivers and a plurality of integrated circuit pads. The up conversion module is operably coupled to convert a low intermediate frequency (IF) signal into a radio frequency (RF) signal. The plurality of drivers are operably coupled to receive the RF signal and to produce separate RF drive signals therefrom. The plurality of integrated circuit pads are coupled to the plurality of drivers to provide the separate RF drive signals to external components of the RFIC.

Abstract: Variable code rate and signal constellation turbo trellis coded modulation (TTCM) codec. A common trellis is employed at both ends of a communication system (in an encoder and decoder) to code and decode data at different rates. The encoding employs a single TTCM encoder whose output bits may be selectively punctured to support multiple modulations (constellations and mappings) according to a rate control sequence. A single TTCM decoder is operable to decode each of the various rates at which the data is encoded by the TTCM encoder. The rate control sequence may include a number of rate controls arranged in a period that is repeated during encoding and decoding. Either one or both of the encoder and decoder may adaptively select a new rate control sequence based on operating conditions of the communication system, such as a change in signal to noise ratio (SNR).

Abstract: A deserializer that deserializes a high data rate bit stream to extract a set of bits contained therein includes a data sampler, a serial-to-parallel converter, a windowing block, and a phase error detection block. The data sampler over samples the high data rate bit stream to produce a serial group of samples corresponding to the set of bits of the high data rate bit stream. The serial-to-parallel converter couples to the data sampler and converts the serial group of samples into a parallel group of samples. The windowing block receives the parallel group of samples and produces output bits corresponding to the set of bits. The phase error detection block couples to the windowing block, detects errors in the alignment of the overlapping sampling windows of the windowing block, and directs the windowing block to adjust the operation. The phase error detection block and the windowing block compensate for bit stream jitter and intersymbol interference.

Abstract: A system reduces unwanted oscillations in a multiple gigabit per second, high gain amplifier portion. The system includes a power source portion having a plurality of power sources and a bias current portion having a plurality of bias current devices. The system also includes an amplification portion having a plurality of amplifiers. A first group of the plurality of amplifiers is coupled to the power source portion and the bias current portion, such that feedback voltage is substantially eliminated to substantially eliminate oscillations in the amplification portion.

Abstract: A multi-mode band-gap current reference includes a band-gap current mode module and an adjustable current source module. The band-gap current module provides a band-gap reference current and a voltage representation of the band-gap reference current. The adjustable current source module is operably coupled to produce a process-independent band-gap current and a voltage representation of the process-independent band-gap current. The adjustable current source module produces the process-independent band-gap current based on a difference between the voltage representation of the band-gap reference current and the voltage representation of the process-independent band-gap current.

Abstract: A test packet generator (225a) within a physical layer device (230) may generate test packets to be communicated over a closed communication path established within the physical layer device (230). The test packets may include a pseudo-random bit sequence. A receiver within the physical layer device (230) may receive at least a portion of the generated test packet. A test packet checker (225b) within the physical layer device may compare at least a portion of the received test packets with at least a portion of the generated test packets in order to determine the bit error rate for the physical layer device. A window counter (225c) within the physical layer device (230) may count at least a portion of a number of bits received within the generated test packets and a number of bits that are in error in at least a portion of the number of bits received.

Abstract: Methods and apparatus for recovering a clock and data from a data signal. A method provides for receiving a clock signal having a first clock frequency and alternating between a first level and a second level, and receiving a data signal having a first data rate, the first data rate equal to the first clock frequency. The method also includes providing a first signal by storing the data signal when the clock signal alternates from the first level to the second level, and providing a second signal by passing the first signal when the clock signal is at the first level, and storing the first signal when the clock signal is at the second level. A third signal is provided by delaying the data signal an amount of time. An error signal is provided by combining the first signal and the third signal, and a reference signal is provided by combining the first signal and the second signal.

Abstract: Presented herein is a run-level split FIFO. According to one embodiment of the present invention, there is presented a method for inverse quantizing. The method comprising receiving a data word; detecting whether the data word comprises a command or run-level data; storing the command, if the data word comprises a command; and processing the run-level data, if the data word comprises run-level data.

Abstract: In an integrated satellite receiver, improved header acquisition techniques are described for quickly locating a header symbol sequence in a data stream substantially implemented on a single CMOS integrated circuit. To identify the location of a header symbol sequence in a data stream, a selected header acquisition technique employs a real time correlator followed by an accumulator. In accordance with an alternative embodiment which reduces the cost very efficiently, a real time correlator is followed by a comparator to pick out and store the top N correlator values from NS symbols in a frame. The timing addresses associated with the stored correlator values are used during an accumulation mode of operation whereby a cumulative memory is used to accumulate the correlator value of each stored timing address. Once accumulation over a predetermined number of frames is finished, the largest or maximum value among the accumulated correlator values is identified.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: An on-chip loop filter includes a 1st resistor, a 1st capacitor, a 2nd capacitor, a 3rd capacitor, a 2nd resistor, and a 4th capacitor. The 1st resistor is operably coupled to receive a charge pump output. The 1st capacitor is coupled in series with the 1st resistor where the second node of the 1st capacitor is coupled to a return. The 2nd capacitor is coupled in parallel with the series combination of the 1st resistor and 1st capacitor. The 3rd capacitor is coupled in parallel with the 2nd capacitor. The 2nd resistor is coupled to a node of the 3rd capacitor and to a node of the 4th capacitor. The other node of the 4th capacitor is coupled to ground.

Abstract: A method for controlling a flow of packet data in a memory management unit of a network switch fabric is disclosed. A first portion of a data packet is received at a port on an ingress bus ring of the network switch fabric. A class of service for the data packet is determined based on the first portion and the portion is stored in a packer RAM of the port based on the class of service. Subsequent portions of the data packet are stored in the packer RAM. Once the predetermined number of portions have been received, the predetermined number of portions is sent to a packet pool RAM. A reference pointer to a first predetermined number of portions is sent to a transaction queue once an end of packet is detected and an egress scheduler detects a presence of a ready packet in the transaction queue and notifies an unpacker of the ready packet. The unpacker puts the ready packet into a FIFO and the ready packet is sent to an ingress/egress module.

Abstract: Phase locked loops that can adjust the frequency of a clock signal are provided. A transmitter adjusts its data transmission rate in response to the clock signal to accommodate different data transmission protocols. A phase locked loop can add or drop cycles from an input clock signal in response to one or more signals from a receiver. The signals from the receiver indicate the transmission rate of the incoming data signal. The phase locked loop can drop cycles from the clock signal to decrease the frequency of the clock signal. The transmitter then decreases its data transmission rate in response to the reduced frequency of the clock signal. The phase locked loop can also add cycles to the clock signal to increase the frequency of the clock signal. The transmitter increases its data transmission rate in response to the increased frequency of the clock signal.

Abstract: A fast starting on-chip crystal oscillation circuit includes a (Vdd) IC pad, a (Vss) IC pad, a 1st crystal IC pad, a 2nd crystal IC pad, a 1st transistor, a 2nd transistor, an inverter, a resistor, and two capacitors. The 1st and 2nd crystal IC pads couple an external crystal oscillator to the fast starting on-chip crystal oscillation circuit. The 1st and 2nd transistors, when activated, couple power to the inverter. The input of the inverter is coupled to the 1st crystal IC pad and to the 1st capacitor. The output of the inverter is coupled to the 2nd crystal IC pad and to the 2nd capacitor. The resistor is coupled in parallel with the inverter. When the 1st and 2nd transistors are activated, an impulse voltage occurs between the 1st and 2nd crystal IC pads to initiate the oscillation of the crystal oscillator.

Abstract: The present invention is directed to a seal structure and a method for forming a seal structure for a semiconductor die. An elongate region which is electrically isolated from the remainder of the substrate, such as a well region of a conductivity type opposite that of the substrate, extends around the major portion of the periphery of the substrate. A gap is left between the two ends of the elongate region along the minor portion of the periphery of the substrate not covered by the elongate region. A conductive seal ring is formed around the periphery of the substrate at the elongate region and spans the gap between the ends of the elongate region. The substrate of the semiconductor die is only brought into electrical contact with the seal ring at the gap between the ends of the elongate region.

Abstract: An on-chip multiple tap transformer balun includes a 1st winding and a 2nd winding having two portions. The 1st winding is on a 1st layer of an integrated circuit and is operably coupled for a single ended signal. The 1st and 2nd portions of the 2nd winding are on a 2nd layer of the integrated circuit. The 1st portion of the 2nd winding includes a 1st node, a 2nd node, and a tap. The 1st node is operably coupled to receive a 1st leg of a 1st differential signal and the 2nd node is coupled to a reference potential. The tap of the 1st portion is operably coupled for a 1st leg of a 2nd differential signal. The 2nd portion of the 2nd winding includes a 1st node, 2nd node, and tap. The 1st node is operably coupled to receive a 2nd leg of the 1st differential signal and the 2nd node is operably coupled to the reference potential. The tap of the 2nd portion is coupled for a 2nd leg of the 2nd differential signal.

Abstract: The present invention provides an apparatus and method to reduce the memory footprint of a processor architecture by structuring processor code to be stored in an external device, and transferring into the processor certain code and associated data as it is needed. The processor code or algorithm is divided into a controlling piece and a working piece. The controlling piece can be located on a low-MIPS, high memory-footprint device, whereas the working piece can be located on a high-MIPS, low memory-footprint device. The working piece can also be broken down into phases or segments, which are put in a data store. The segments are then transferred, on an as-needed basis along with associated data, from the store into the constrained memory of the low memory-footprint device. Transfer is facilitated by a segment manager which can be processed from the low-MIPS device, or alternatively from the high-MIPS device.

Abstract: A buffer architecture and latency reduction mechanism for buffering uncompressed/compressed information. This combination provides for proficient division of the encoding task and quicker through put time. A single chip digital signal processing device for real time video/audio compression comprises a plurality of processors, including a video input processor, a motion estimation processor, a digital signal processor, and a bitstream processor, wherein processing and transfer of the signals within the device is done in a macroblock-by-macroblock manner. The device can include a multiplexing processor that is comprised of a storage unit which buffers a compressed video bitstream and a processor which retrieves the compressed video bitstream from the storage unit and produces a multiplexed data stream whereby the compressed video bitstream is processed in a pipeline manner.

Abstract: A system, method and computer program product is provided for mitigating the effects of burst noise on packets transmitted in a communications system. A transmitting device applies an outer code, which may include, for example, a block code, an exclusive OR (XOR) code, or a repetition code, to one or more packets prior to adaptation of the packets for transmission over the physical (PHY) layer of the communications system, wherein the PHY layer adaptation may include FEC encoding of individual packets. The outer coded packets are then separately transmitted over a channel of the communications system. A receiving device receives the outer coded packets, performs PHY level demodulation and optional FEC decoding of the packets, and then applies outer code decoding to the out6r coded packets in order to restore packets that were erased during transmission due to burst noise or other impairments on the channel.

Abstract: A receiver comprises a first Variable Gain Amplifier (VGA) that amplifies an input signal in accordance with a first gain to produce a first amplified signal. The first gain is controlled based on the first amplified signal. The receiver includes a second VGA that produces a second amplified signal responsive to the first amplified signal. The second VGA has a second gain controlled based on the second amplified signal.