Abstract: An apparatus and method for switching VOIP packets in a data network, wherein the method includes the steps of receiving a first packet in a network switch and determining if the first packet is a VOIP packet. Further, method includes determining a dynamically negotiated VOIP port for a VOIP session from at least one of the first packet and a second packet received in the network switch, if the first packet is determined to be the VOIP packet. Finally, the method includes the steps of classifying all subsequent VOIP packets corresponding to the dynamically negotiated VOIP port in accordance with predetermined parameters. The apparatus includes a network switch having at least one data port interface controller supporting a plurality of data ports for transmitting and receiving data, and a fast filtering processor in communication with the at least one data port interface.

Abstract: Often programmable gain attenuators (PGAs) are combined with high pass filters. Adjustment of the highpass filter however can have unintended effects, such as changing the step size of the PGA. By placing the resistance of the highpass filter in parallel with a programmable attenuator divider, the steps of the PGA can be minimally affected as the highpass frequency is adjusted.

Abstract: Modular, portable data collection terminals are disclosed for use in mixed wireless and hard-wired RF communication networks, wherein various radio transmitter modules and associated antennas may be selectively added to a base terminal unit to solve networking problems associated with specific types of business environments. Modularity exists in both the hardware (splitting data collection and processing control circuitry from radio transceiver control circuitry) and software (splitting transceiver-specific, lower level communication protocol from generic, higher level communication protocol). The control circuitry, including associated microprocessors devices, interact to selectively activate communication circuits to perform necessary communication or data processing functions and enter and remain in a power-saving dormant state during other times. To support such dormant or “sleeping” states, a series of communication protocols provide for channel access to the communication network.

Abstract: A hierarchical memory structure having memory cells, and sense amplifiers and decoders coupled with the memory cells to form first tier memory module, and subsequent tiers being formed by having (n?1)-tier memory modules, which are coupled with (n)-tier sense amplifiers and (n)-tier decoders. Also provided are a single-ended sense amplifier having sample-and-hold reference, and a charge-share limited-swing-driver sense amplifier; an asynchronously-resettable decoder; a wordline decoder having row redundancy; a redundancy device having redundant memory cells operated by a redundancy controller; a diffusion replica delay circuit; a high-precision delay measurement circuit; and a data transfer bus circuit imposing a limited voltage swing on a data bus. Methods are provided for a write-after-read operation without an interposed precharge cycle, and write-after-write operation with an interposed precharge cycle are provided, either operation being completed in less than one memory access cycle.

Abstract: A low-speed DLL facilitates a deskewed interface between a high-speed RX data demultiplexer circuit directly to an Application Specific Integrated Circuit (ASIC) with which it is integrated by locking a 156 MHz ASIC clock to a 156 MHz reference derived from a high speed 2.5 GHz clock. The DLL employs a digital interpolator to generate 32 phases of the 156 MHz clock. The digital interpolator supplies the phases using a double clocked shift register with recirculating feedback. The shift register is double clocked using the 2.5 GHz clock. The register outputs are tapped and fed to a 32:1 multiplexer having a phase select input that is controlled by the phase difference signal generated by the DLL. The phase difference control signal is converted to a digital representation of its magnitude by which the requisite number of phase shift increments may be selected.

Abstract: A method, system, and a computer program product for filtering palettized image formats are presented. In an embodiment, data is retrieved from a palette of an image. Data associated with a channel of the palette is filtered, and stored, for example, together with a pixel buffer of the image to form a filtered image. Additionally, a method, system, and a computer program product for displaying images stored in a modified palettized image format are presented. In an embodiment, data is retrieved from a palette and from a pixel buffer of an image stored in modified palettized image format. Filtered pixels of the image are formed by combining, for each pixel in the pixel buffer, data retrieved from the palette with filtered data, retrieved from the pixel buffer. The modified palettized image is rendered on a display by displaying the filtered pixels.

Abstract: Systems and methods for pulse stretching architectures for phase alignment of multi-frequency clocks for high speed data acquisitions are disclosed. A high speed data acquisition system includes a transmitter and a receiver. The receiver includes a multi-frequency clock generator that generates a plurality of clock signals, a pattern check module that detects a test pattern received from the transmitter and outputs a stretch command signal, and a stretch pulse generator that receives the stretch command signal and provides a stretch pulse signal that aligns the phases of the plurality of clock signals generated by the multi-frequency clock generator. Methods for initializing and shifting multi-phase clock signals to optimize error performance of a high speed data acquisition system are also provided.

Abstract: A super set of orthogonal space-time block codes is combined with set partitioning to form super-orthogonal space-time trellis codes having full diversity, enhanced coding gains, and improved rates. In communications systems, these codes are implemented by an encoder of a diverse transmitter to send an information signal to a receiver having one or more receiver elements. A decoder in the receiver decodes the encoded signal to reproduce the information signal. A method of the invention is used to generate set portioning structures and trellis structures that enable code designers to systematically design the codes of the invention.

Abstract: A system and method use an aligning device to align clock signals of two logic devices before data transfer between them. In this example, the aligning device aligns a clock signal of a sequencer with a clock signal of a storage device before the sequencer transfers data to the storage device. The aligning device includes a phase detector that receives a first reference clock signal, which is used to control the storage device, and a delayed signal, which is used to control the sequencer, and generates a comparison clock signal. The comparison clock signal is filtered before being used to control a phase of a second reference clock signal, which is related to the first reference clock signal. The phase controlled second clock signal is an aligning clock signal that is feed back to a delay device to produce one or more subsequent delay device clock signals that are aligned to the storage device clock or first reference clock signal.

Abstract: A point-to-multipoint network interface is provided that is simpler and less costly to implement than conventional Ethernet switches. The interface includes a plurality of downstream transmitters for transmitting data packets to a plurality of end user devices, a plurality of downstream receivers for receiving data packets from the plurality of end user devices, an upstream transmitter and an upstream receiver. A multiplexer within the interface multiplexes data packets received from the end user devices into a stream of data packets for transmission to a higher level node regardless of the destination address of the data packets. Conversely, a demultiplexer within the interface demultiplexes a stream of data packets received from the higher level node into individual data packets for selective transmission to one of the plurality of end user devices. The interface can support asymmetrical transmission rates on the upstream and downstream channels between the interface and the end user devices.

Abstract: A system and method of assembling a ball grid array (BGA) package with IC die support is described. A stiffener is attached to a substrate that includes a centrally located opening with an integrated circuit (IC) die support structure removably held therein. An IC die is mounted to a central region of the stiffener. Further assembly process steps may be performed on the BGA package with IC die support. The IC die support structure is removed from the centrally located opening. In aspects of the invention, the IC die support structure is removably held in the opening by an adhesive tape or by one or more substrate tabs.

Abstract: A programmable multi-stage amplifier includes a 1st programmable amplifier, a 2nd programmable amplifier, and a control module. The 1st and 2nd programmable amplifiers are coupled in series to amplify an input signal. Each of the 1st and 2nd programmable amplifiers is operably coupled to receive independent gain control signals from the control module. The control module generates the gain control signals by determining the overall gain desired for the programmable multi-stage amplifier and a corresponding gain for each of the 1st and 2nd programmable amplifiers. The factors in which the control module makes this determination are based on an optimization of at least one of the power level of the programmable multi-stage amplifier, the noise factor for the programmable multi-stage amplifier, and/or linearity of the programmable multi-stage amplifier.

Abstract: An on chip diversity antenna switch includes a first switch, a second switch, a third switch, and a fourth switch. The first switch is operably coupled to a pin associated with a first antenna, to a transmit path and to receive a transmit receive (T/R) control signal. The second switch is operably coupled to the pin associated with the first antenna, to a receive path, and to receive the T/R control signal. The third switch is operably coupled to a pin associated with a second antenna, the transmit path, and to receive the T/R control signal. The fourth switch is operably coupled to the pin associated with the second antenna, to the receive path, and to receive the T/R control signal. Based on the T/R control signal, the first or second antenna is coupled to the transmit or receive path via a single switch.

Abstract: Methods and systems for on-chip processing of data are disclosed. Aspects of the method may include generating a plurality of data processing commands for data compression. A first string of characters may be encoded in one operating cycle utilizing the generated plurality of data processing commands for data compression. The plurality of data processing commands may comprise a branch command, a register moving command, a register setting command, a memory load command, a memory store command, and/or a register compare command. The generated plurality of data processing commands may be stored. At least a portion of the stored data processing commands may be decoded. The decoded portion of the stored data processing commands may be sequenced. The first string of characters may be acquired from a character space. The acquired first string of characters may be matched with at least one existing codeword.

Abstract: A modifiable circuit for coupling at least two adjacent logic blocks in an integrated circuit chip is disclosed. The chip includes a plurality of metal layers and first and second power supply potentials. The circuit comprises a first and second metal interconnect structures, and an interconnect. The first metal interconnect structure traverses the plurality of metal layers using a first plurality of vias, wherein the first metal interconnect structure is located at a boundary of the at least two adjacent logic blocks. The second metal interconnect structure traverses the plurality of metal layers using a second plurality of vias, wherein the second metal interconnect structure is located at the boundary of the at least two adjacent logic blocks.

Abstract: A data processor comprising: a register memory comprising an array of memory cells extending in two dimensions, the cells being located on rows in the first dimension and columns in the second dimension, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the row and column of the cell in the array; and a processing unit capable of executing instructions that operate on a plurality of memory cells in the register, the instructions identifying the plurality of cells by means of a first instruction part specifying a pair of coordinates that identify a first cell in the array, and a second instruction part that identifies the configuration of the plurality of cells relative to the first cell; the data processor being arranged to interpret a first form of second instruction part as specifying a first group of cells all of which are located in the same row but in different columns, and to interpret a second form of second instruction part as specifying a first grou

Abstract: An error compensation bias circuit and method for a canonic signed digit (CSD) fixed-width multiplier that receives a W-bit input and produces a W-bit product. Truncated bits of the multiplier are divided into two groups (a major group and a minor group) depending upon their effects on quantization error. An error compensation bias is expressed in terms of the truncated bits in the major group. The effects of the remaining truncated bits in the minor group are taken into account by a probabilistic estimation. The error compensation bias circuit typically requires only a few logic gates to implement.

Abstract: Systems and methods are disclosed for arbitrating requests from a plurality of clients requesting access to a shared real-time resource. In one embodiment, a plurality of sub-clients are aggregated into an aggregate client. At the aggregate client, access requests from the sub-clients are arbitrated to generate an aggregate request. An aggregate deadline is determined and access requests from the aggregate client and other clients are arbitrated using the aggregate deadline as the deadline of the aggregate client. In one embodiment, a critical instant analysis of the system is performed using the aggregate deadline as the deadline of the aggregate client. In another embodiment, a block-out counter is employed at an aggregate client to regulate the rate at which the aggregate client provides access requests to the shared resource.

Abstract: An FM radio receiver includes a low noise amplifier, down conversion mixing module, local oscillation module, bandpass filter, demodulation module, and a DC offset estimation module. The low noise amplifier, the down conversion mixing module, the bandpass filter, and the demodulation module are operably coupled to recapture data from a received a radio frequency (RF) signal. The local oscillation module is operably coupled to generate the local oscillation based on a reference oscillation and a DC offset correction signal. The DC offset estimation module is operably coupled to generate the DC offset correction signal based on a determined a DC offset. The DC offset estimation module determines the DC offset prior to compensation of the local oscillation, such as during a test sequence and/or during a preamble.

Abstract: A transceiver circuit having 10 mb and 100 mb transmit and receive circuitries using the power saving methods allows for power consumption of the transceiver circuit to be significantly reduced. This is accomplished by providing each defined subcircuit with its own power supply and means of activation and deactivation. However, the method for activating and deactivating digital subcircuits and analog subcircuits are different and therefore different types of control signals and methods are provided. Furthermore, there are two general types of power-saving situations. The first type is near total circuit power-down and the second type is partial circuit power-down. In yet another embodiment, a method for minimizing energy usage during the idle period is utilized.