Abstract: A number of features for enhancing the performance of a cable transmission system in which data is transmitted between a cable modem termination system at a headend and a plurality of cable modems located different distances from the headend. The power transmission level, slot timing, and equalization of the cable modems are set by a ranging process. Data is transmitted by the modems in fragmented form. Various measures are taken to make transmission from the cable modems robust. The upstream data transmission is controlled to permit multiple access from the cable modems.

Abstract: The present invention provides an efficient method for near-unity sampling rate alteration in high performance applications, such as CD to DAT conversion. Specifically, the input digital signal is first interpolated by a factor of eight and lowpass filtered to form an intermediate signal. A clamped cubic spline interpolator (CCSI) algorithm is then employed to accurately interpolate the intermediate signal to points in-between adjacent samples of the intermediate signal as required by the 48 kHz output sampling rate. The CCSI is highly accurate due to highly accurate derivative estimates arrived at by repeated Richardson extrapolation. In the example CD to DAT converter covered in detail, fourth order Richardson extrapolation is employed. It is shown by this example that the proposed method yields the desired performance, is computationally efficient and requires little storage.

Abstract: A design of integrated circuit components to prevent accidental turn on when large input signals are accepted. With integrated circuits operated at lower power supply voltages, input signals having large peak values can tend to turn on devices within the integrated circuit erroneously. By placing amplifiers within the integrated circuits where input signals are received and removing the power of such amplifiers, accidental turn on can be minimized.

Abstract: An electrically and thermally enhanced die-up tape substrate ball grid array (BGA) package and die-up plastic substrate BGA package are described. A substrate that has a first surface and a second surface is provided. The stiffener has a first surface and a second surface. The second stiffener surface is attached to the first substrate surface. An IC die has a first surface and a second surface. The first IC die surface is mounted to the first stiffener surface. A plurality of solder balls is attached to the second substrate surface. In one aspect, a heat spreader is mounted to the second IC die surface. In another aspect, the stiffener is coupled to ground to act as a ground plane. In another aspect, the substrate has a window opening that exposes a portion of the second stiffener surface. The exposed portion of the second stiffener surface is configured to be coupled to a printed circuit board (PCB). In another aspect, a metal ring is attached to the first stiffener surface.

Abstract: A multi-modulus divider for producing a low-noise divided output, wherein one embodiment comprises a low-noise frequency divider comprising a pulse-swallow configured divider module and first, second, and third latching blocks. The pulse-swallow configured divider module produces a pre-scaled divider output and a divided oscillation. The divided oscillation is sequentially latched by the latching blocks, wherein the divided oscillation and pre-scaled divider output, coupled as clocks to the latching blocks, resynchronize the divided oscillation to substantially eliminate noise. The first and second latching blocks are biased by a first bias signal and the third latching block is biased by a second bias signal wherein the second bias signal is larger than the first bias signal. Each latching block includes an output load device wherein the impedance of the third latching block is smaller than the impedance of the other output load devices.

Abstract: A transceiver includes a transmitter portion with an analog modulator that modulates data using frequency shift keyed (FSK) modulation techniques to increase efficiency, reduce power consumption, and reduce IC real estate in comparison to current digital FSK modulation circuits. The analog modulator comprises a loop that includes a pair of integrators and a pair of mixers. In at least one embodiment, the pair of mixers comprises switches that control a polarity of a modulated output signal that is produced to an up-conversion module for up-conversion to RF. The up-conversion module, then, when mixing the modulated output signal with a local oscillation signal, produces an output having one of two possible frequencies wherein the frequencies are a function of the polarity of the modulated output signal.

Abstract: Certain embodiments for ensuring the assertion order of signals in a chip independent of physical layout may comprise receiving a first signal by a first logic block of a plurality of logic blocks integrated within a chip, where the first signal may initiate a reset of a first function within the first logic block. A second signal may be communicated from within the first logic block to a second function within a second logic block of the plurality of logic blocks, and the second signal may be adapted to initiate the second function. The first signal may be the same as a second signal. The reset of the first function may initialize the first function to a known state before the second function may generate an output that may be received by the first function. The first function may place the chip in a test mode when indicated by the generated output of the second function.

Abstract: A system and method for efficiently detecting and decoding valid teletext message sequences is provided. A system is provided that includes a correlator, a sine wave generator, two time window generators, a phase detector, a framing code search engine, and a match filter. The method includes determining the phase of the run-in burst of a teletext message sequence, identifying the framing code location, deciding whether the teletext sequence is valid, and decoding the teletext data for display.

Abstract: The present invention provides a frequency-diverse single-carrier modulation scheme that extends the usable SNR range of severely distorted channels. This scheme is advantageous for applications in which when the SNR is low and the transmitted spectrum contains unusable regions (e.g., spectral nulls due to radio-frequency interference ingress or egress). In one embodiment, the symbol baud rate is selected in order that unusable portions of the frequency response of the transmission channel are mapped onto usable portions of the frequency response of the transmission channel.

Abstract: Method and circuitry for improving the accuracy and efficiency of a phase-locked loop. More specifically, the present invention relates to a method and device for monitoring the frequency discrepancy between two signals in conjunction with at least one data signal so as to improve the accuracy and efficiency of a phase-locked loop. In one embodiment of the present invention, two counters are used to check the frequency differential between a VCO signal and an external reference or input signal. An adjustable threshold is provided to determine whether the frequencies of the two signals are considered to be in a frequency-locked mode. A pair of flip-flops is used to minimize any erroneous detection of frequency discrepancy by validating two consecutive results of the frequency differential check. In addition, a data present signal is used to control the transition between the phase-locked mode and the frequency-locked mode to minimize the potential data loss.

Abstract: An RF communications system includes a transmit node for transmitting an RF information signal and a receive node for receiving the transmitted RF information signal. The receive node includes a passive mixer coupled to an amplifier for producing an IF or baseband differential mixer output signal as a function of a LO drive signal. The passive mixer having a first plurality of transistors of a first polarity type arranged in a ring configuration and a second plurality of transistors of a second polarity type, wherein each of second plurality of transistors is coupled to one of said first plurality of transistors.

Abstract: A mechanism and method for redefining an application specific integrated circuit's I/O bus structure in real-time. The mechanism includes an address map block, a state machine block, and a bus arbitration block. At initialization, the address map is configured to divide the address space into regions and type of bus structure. When an I/O access is requested by a client (e.g., CPU, DMA controller, etc.), the request is mapped into a region and type of bus structure by the address map block. The region and type of bus structure is used by the state machine. The state machine determines the syntax and protocol for the region and type of bus. The state machine signals the bus arbitration block to grant I/O bus ownership when it is available. Once ownership is granted, I/O bus pins are defined and access is granted.

Abstract: A mixer for a radio transceiver includes a commutating mixer switch having a first differential input port coupled to a DC offset cancellation path. The first differential input port of the mixer switch includes a first terminal coupled to a first end of a first resistor and a second terminal coupled to a first end of a second resistor. Second ends of the first and second resistors are configured to receive a differential input signal. The DC offset cancellation path may provide a resistively coupled DC calibration signal for reducing the magnitude of DC offsets that may be present at the input of the mixer switch. The concept can be used for either image or non-image reject mixers.

Abstract: An ADSL transceiver chip is provided that includes an analog front-end and a digital signal processor (DSP) integrated on the same substrate. A line driver for the ADSL transceiver can be located on a separate substrate. In embodiments of the invention, the transceiver chip is implemented in a CMOS process. For example, the process could be a low voltage CMOS process. It is highly advantageous to build the analog front-end and the DSP on a single integrated IC because it allows for reduced manufacturing part count, reduced assembly time and cost. Furthermore, the line driver substrate can require a high voltage semiconductor process (e.g. 18 volts peak-to-peak) in some applications, because of the need for adequate voltage to drive the ADSL line. Whereas, the analog front-end and the DSP do not need the such a high-voltage process as required for the by the line driver 102. For example, the analog front-end and DSP can operate with 3.3 v or 5.

Abstract: A virtual tester that simulates automatic test equipment (ATE). A translator converts program code of the ATE to pattern information and timing information. The virtual tester tests a software representation of a circuit, based on the program code of the ATE. The virtual tester uses the pattern information and/or the timing information to test the software representation of the circuit.

Abstract: A method of handling data packets in a series of network switches is disclosed. An incoming data packet is received at a data port of a first switch of the series of network switches and a stack tag is resolved from a header of the incoming data packet. It is then determinined whether an incoming data packet is a unicast packet, a multicast packet or an IP multicast packet; and the address resolution lookup and layer three IP lookup tables are searched to find an egress port for the incoming data packet. The packet header is modified and the packet is forwarded to at least a second switch of the series of network switches, on a stacked connection operating at a first data rate, based on the stack tag and the egress port. The header is later remodified when the egress port is one of a series of data ports of a particular switch of the series of switches.

Abstract: A network switch for network communications includes at least one first data port interface, wherein the a least one first data port interface supports a plurality of first data ports transmitting and receiving data at a first data rate. At least one second data port interface is provided, wherein the at least one second data port interface supports a plurality of second data ports transmitting and receiving data at a second data rate. A flow control unit is provided, wherein at least one of the first data ports and at least one of the second data ports are linked together with a plurality of ports on a second network switch forming a trunk group that is configured by the flow control unit to statistically distribute a data load transmitted across the trunk group.

Abstract: A method for decoding a received word, including calculating a syndrome of the received word as a plurality of binary element vectors, generating respective logarithms of the binary element vectors, and determining, in response to the logarithms, an indication of a position of an erroneous bit in the received word.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, and graphics input. The chip includes a single polyphase filter that preferably provides both anti-flutter filtering and scaling of graphics. Anti-flutter filtering may help reduce display flicker due to the interlaced nature of television displays. The scaling of graphics may be used to convert the normally square pixel aspect ratio of graphics to the normally rectangular pixel aspect ratio of video.

Abstract: A precision tunable VCO includes a bias transistor, a first inductor, a second inductor, a first input transistor, a second input transistor, a first capacitor, a second capacitor, a first precision tune capacitor circuit, and a second precision tune capacitor circuit. The bias transistor, the first and second inductors, the first and second input transistors, and the first and second capacitors are operably coupled to produce a differential output oscillation. The first precision tune capacitor circuit is operably coupled to the first leg of the differential output oscillation, wherein the first precision tune capacitor circuit provides a first precision capacitance value based on a calibration signal.