Patents Assigned to Broadcom Corporation
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Publication number: 20030218556Abstract: An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.Type: ApplicationFiled: February 6, 2003Publication date: November 27, 2003Applicant: Broadcom CorporationInventors: Franciscus Maria Leonardus van der Goes, Jan Mulder, Christopher Michael Ward, Jan Roelof Westra, Rudy van de Plassche, Marcel Lugthart
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Publication number: 20030220956Abstract: An error compensation bias circuit and method for a canonic signed digit (CSD) fixed-width multiplier that receives a W-bit input and produces a W-bit product. Truncated bits of the multiplier are divided into two groups (a major group and a minor group) depending upon their effects on quantization error. An error compensation bias is expressed in terms of the truncated bits in the major group. The effects of the remaining truncated bits in the minor group are taken into account by a probabilistic estimation. The error compensation bias circuit typically requires only a few logic gates to implement.Type: ApplicationFiled: April 23, 2003Publication date: November 27, 2003Applicant: Broadcom CorporationInventors: Keshab K. Parhi, Jin-Gyun Chung, Sang-Min Kim
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Publication number: 20030218560Abstract: An analog to digital converter includes a first amplifier array connected to taps from a reference ladder, a second amplifier array, wherein each amplifier in the first amplifier array is connected to only two amplifiers of the second amplifier array, a third amplifier array, wherein each amplifier in the second amplifier array is connected to only two amplifiers of the third amplifier array, and an encoder connected to outputs of the third amplifier array that converts the outputs to an N-bit digital signal.Type: ApplicationFiled: June 13, 2003Publication date: November 27, 2003Applicant: Broadcom CorporationInventors: Jan Mulder, Christopher Michael Ward
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Patent number: 6653901Abstract: A system is provided for correcting start-up deficiencies in an amplifier. The system includes a comparing device configured to (i) receive a second circuit node voltage and a reference voltage as inputs, (ii) compare the received second circuit node voltage and the reference voltage, and (iii) produce a compensating voltage signal based upon the comparison. Next, an active device has a control terminal connected to an output port of the comparing device and is configured to receive the compensating voltage signal. The active device also includes an output terminal connected to the control terminal of the second active device, and a common terminal connected to a first circuit node. Another active device has a control terminal connected to the output port of the comparing device and is configured to receive the compensating voltage signal. The other active device also has an output terminal connected to the control terminal of the first active device, and a common terminal connected to the first circuit node.Type: GrantFiled: January 9, 2003Date of Patent: November 25, 2003Assignee: Broadcom CorporationInventor: David A. Sobel
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Patent number: 6653966Abstract: An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.Type: GrantFiled: February 6, 2003Date of Patent: November 25, 2003Assignee: Broadcom CorporationInventors: Franciscus Maria Leonardus van der Goes, Jan Mulder, Christopher Michael Ward, Jan Roelof Westra, Rudy van de Plassche, Marcel Lugthart
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Patent number: 6653876Abstract: A method and apparatus are disclosed for efficiently doubling a first frequency of a first clock signal. A second clock signal at a second frequency is generated by dividing the first frequency of the first clock signal by two, such that the second frequency is half of the first frequency and a duty cycle of the second clock signal is 50%. Also, a set of phase-delayed clock signals is generated in response to the second clock signal such that the set of phase-delayed clock signals are delayed in phase with respect to the second clock signal. Further, the set of phase-delayed clock signals is combined to generate a third clock signal at a third frequency, such that the third frequency is twice that of the first frequency and a duty cycle of the third clock signal is 50%.Type: GrantFiled: April 23, 2002Date of Patent: November 25, 2003Assignee: Broadcom CorporationInventors: Sami Issa, Morteza (Cyrus) Afghahi
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Publication number: 20030217235Abstract: An apparatus comprises a first plurality of buffers configured to store operations belonging to a first virtual channel and a control circuit coupled to the first plurality of buffers. The first virtual channel includes first operations and second operations, wherein each of the first operations depend on at least one of the second operations during use. A first number of the first operations is less than or equal to a maximum. It is ambiguous, for a first received operation in the first virtual channel, whether the first received operation is one of the first operations or the second operations. A total number of the first plurality of buffers exceeds the maximum.Type: ApplicationFiled: May 9, 2003Publication date: November 20, 2003Applicant: Broadcom CorporationInventor: Joseph B. Rowlands
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Publication number: 20030215027Abstract: Quadrature receiver sampling architecture. A signal ADC performs analog to digital conversion for both I and Q streams. An analog MUX selects the appropriate I and the Q baseband analog input streams for input to the ADC at the appropriate time. A digital filter may also be employed to compensate for any introduced delay between the samples of the I and Q channel when seeking to recover the symbols that have been transmitted to a communication receiver that employs this quadrature receiver architecture and/or signal processing. In one embodiment, if an ADC is clocked at a rate of substantially twice the sample rate of the I and Q channels, there will be a one-half sample clock delay between the digital I and digital Q data at the output of the ADC. This delay is then removed before the demodulator processes the input signals to recover the transmitted symbols.Type: ApplicationFiled: June 28, 2002Publication date: November 20, 2003Applicant: Broadcom Corporation ,a California CorporationInventors: Tommy Yu, Steven Jaffe, Stephen Edward Krafft
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Publication number: 20030217115Abstract: A node includes a processor coupled to an interconnect and a memory bridge coupled to the interconnect. The processor is configured to maintain a first indication of whether or not a modification of data at a first address has been detected by the processor after a most recent load-linked (LL) instruction was executed by the processor to the first address. The memory bridge is responsible for internode coherency within the node, and is configured to initiate a first transaction on the interconnect in response to receiving a probe command from another node. The processor is configured, during a time period in which the processor has a second transaction outstanding to the first address, to change the first indication to the first state responsive to the first transaction.Type: ApplicationFiled: May 9, 2003Publication date: November 20, 2003Applicant: Broadcom CorporationInventor: Joseph B. Rowlands
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Publication number: 20030217229Abstract: A cache comprises a memory including a plurality of entries and a circuit. Each entry of the plurality of entries is configured to store a cache block. The circuit is configured to select a first entry of the plurality of entries to store a first cache block. In one implementation, the first cache block corresponds to a first transaction initiated by a first agent, wherein the first entry is selected from a first subset of the plurality of entries indicated as selectable for the first agent. In another implementation, the circuit is configured to select the first entry of the plurality of entries in response to whether the first cache block is a remote cache block or a local cache block. In other implementations, the circuit may be configured to handle a combination of the above.Type: ApplicationFiled: April 15, 2003Publication date: November 20, 2003Applicant: Broadcom CorporationInventors: Joseph B. Rowlands, Rohini Krishna Kaza
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Publication number: 20030214982Abstract: A system for adding a time stamp to transmission traffic on a network comprises a front end processor that receives a packet from the network and generates a Start Of Frame pulse and a LENGTH field corresponding to a length of the packet. A time stamp generator generates a time stamp by sampling the system master time counter. A synchronizer receives the SOF pulse and the LENGTH field from the front end processor, and generates a control signal. A multiplexer inputs the packet from the front end processor, the control signal and the time stamp, and outputs a modified packet with a field in the packet replaced by the time stamp.Type: ApplicationFiled: October 30, 2002Publication date: November 20, 2003Applicant: Broadcom CorporationInventors: John Lorek, David R. Dworkin
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Publication number: 20030217238Abstract: A node comprises an interconnect, circuitry coupled to the interconnect and configured to initiate a transaction on the interconnect, and a control circuit coupled to provide a response to the transaction on the interconnect. The transaction addresses a block, and the response is indicative of a state of the block in one or more other nodes. The control circuit is configured to cause the transaction to become globally visible to the one or more other nodes dependent on the state in the one or more nodes. Using one or more communication lines separate from lines used to initiate transactions, the control circuit is configured to transmit an indication of the transaction on the interconnect responsive to the transaction becoming globally visible. A transfer of data on the interconnect for the transaction is delayed, responsive to the response from the control circuit, until the indication is transmitted by the control circuit.Type: ApplicationFiled: April 15, 2003Publication date: November 20, 2003Applicant: Broadcom CorporationInventors: Joseph B. Rowlands, Koray Oner
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Patent number: 6650880Abstract: A wireless (radio) receiver receives RF signals carrying data synchronized with a first clock. The wireless receiver demodulates the RF signals to extract the data signals and the first clock signals. The wireless receiver uses the first clock signals as write signals to write the data signals in a first-in first-out memory device (FIFO). The data signals stored in the FIFO may be read out with read signals synchronized to a second clock. In one example, a host associated with the wireless receiver reads out data signals stored in the FIFO with read signals synchronized to the system clock of the host receiver. In another example, the wireless receiver includes a data processing circuit (e.g., including forward error correction, de-whitening, and cyclical redundancy check circuits) that reads out data signals stored in the FIFO with read signals synchronized to the system clock of the wireless receiver.Type: GrantFiled: June 12, 2000Date of Patent: November 18, 2003Assignee: Broadcom CorporationInventors: Sherman Lee, Vivian Y. Chou, John H. Lin
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Patent number: 6650624Abstract: A number of features for enhancing the performance of a cable transmission system in which data is transmitted between a cable modem termination system at a headend and a plurality of cable modems located different distances from the headend. The power transmission level, slot timing, and equalization of the cable modems are set by a ranging process. Data is transmitted by the modems in fragmented form. Various measures are taken to make transmission from the cable modems robust. The upstream data transmission is controlled to permit multiple access from the cable modems.Type: GrantFiled: May 19, 2000Date of Patent: November 18, 2003Assignee: Broadcom CorporationInventors: Thomas J. Quigley, Jonathan S. Min, Lisa V. Denney, Henry Samueli, Sean F. Nazareth, Feng Chen, Fang Lu, Christopher R. Jones
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Patent number: 6650572Abstract: The method and system of the present invention superimposes read and write operations by connecting the global bit lines that are not selected to the Vdd. As a result, the respective local sense amplifiers for the non-selected global bit lines will just read and refresh the respective memory cells. This new approach results in smaller local sense amplifiers and one global sense amplifiers for several memory cells (and local sense amplifiers). In one embodiment, eight global bit lines are shared by one global sense amplifier and multiplexed to achieve the advantages of the present invention. Due to an analog global multiplexing scheme used by the present invention, only one global bit line pair generates voltage development as an input to a respective local sense amplifier during a write operation, while the other three global bit line pairs are disconnected from their respective local sense amplifiers and thus have no voltage development.Type: GrantFiled: August 21, 2002Date of Patent: November 18, 2003Assignee: Broadcom CorporationInventor: Sami Issa
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Patent number: 6650267Abstract: The output of each cell in an A-D converter on an IC chip is dependent upon the relative values of an input voltage and an individual one of progressive fractions of a reference voltage respectively introduced to the branches in a differential amplifier. To minimize output errors from cell mismatches, first and second sets of averaging impedances, preferably resistors, are respectively connected between the output terminals in the first branches, and the output terminals in the second branches, in successive pairs of cells. The impedances have relatively low values, particularly compared to the impedances of current sources connected to the branch output terminals. First and second resistive strips on the chip may be tapped at progressive positions to respectively define the impedances in the first and second sets.Type: GrantFiled: May 15, 2002Date of Patent: November 18, 2003Assignee: Broadcom CorporationInventors: Klaas Bult, Aaron W. Buchwald
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Patent number: 6650167Abstract: Systems and methods are disclosed for a multi-level level shifter circuit having a single ended input and adapted to translate one or more signals from one voltage level to another. More specifically, the present invention provides a level shifter that doesn't require a complementary input or an additional power supply if the complementary signal isn't available. One embodiment of the level shifter circuit device having a single-ended input comprises at least three transistor devices. The first transistor device is coupled to at least the input and is adapted to have a threshold voltage less than 0V. The second transistor device is coupled to at least the first transistor device, while a level shifter transistor device is coupled to at least the first and second transistor devices.Type: GrantFiled: June 6, 2002Date of Patent: November 18, 2003Assignee: Broadcom CorporationInventors: Darrin Benzer, Robert F. Elio
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Patent number: 6650563Abstract: A compact dynamic random access memory (DRAM) cell and highly efficient methods for using the DRAM cell are disclosed. The DRAM cell provides reading, writing, and storage of a data bit on an ASIC chip. The DRAM cell includes a first transistor acting as a pass gate and having a first source node, a first gate node, and a first drain node. The DRAM cell also includes a second transistor acting as a storage device and having a second drain node that is electrically connected to the first drain node to form a storage node. The second transistor also includes a second source node and a second gate node. The second source node is electrically floating, thus increasing the effective storage capacitance of the storage node.Type: GrantFiled: April 23, 2002Date of Patent: November 18, 2003Assignee: Broadcom CorporationInventor: Sami Issa
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Patent number: 6650196Abstract: A variable frequency output signal is generated in response to a control signal by providing an oscillator (50) that generates the output signal in different frequency ranges depending on the value of an operating parameter, such as DC bias current. A first circuit (60) adjusts the operating parameter values and a second circuit (80) controls the Kvco of the oscillator.Type: GrantFiled: September 28, 2001Date of Patent: November 18, 2003Assignee: Broadcom CorporationInventor: Andrew D. Nguyen
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Publication number: 20030210086Abstract: A circuit and a method for limiting a voltage to a specified value (e.g., a rail voltage) without clipping thereby includes a pair of MOSFETs that turn on when a specified bias voltage is reached to either add to or sink current from the input node of the resistive load responsive to fluctuations in current going through the output resistive load to maintain a constant current through it. A plurality of biasing circuits is provided that control the turn on voltage levels for the MOSFETs to achieve the desired operation. The biasing circuits include circuit components that are matched to circuit components within the circuitry that adds and drains current to the output resistive load including a resistive load that matches the output resistive load.Type: ApplicationFiled: May 12, 2003Publication date: November 13, 2003Applicant: Broadcom Corporation, a California CorporationInventor: Mike Kappes