Abstract: IPHD (Iterative Parallel Hybrid Decoding) of various MLC (Multi-Level Code) signals. Various embodiments are provided by which IPHD may be performed on MLC LDPC (Multi-Level Code Low Density Parity Check) coded modulation signals mapped using a plurality of mappings. This IPHD may also be performed on MLC LDPC coded modulation signals mapped using only a singe mapping as well. In addition, various embodiments are provided by which IPHD may be performed on ML TC (Multi-Level Turbo Code) signals. These principles of IPHD, shown with respect to various embodiments IPHD of MLC LDPC coded modulation signals as well as the IPHD of ML TC signals, may be extended to performing IPHD of other signal types as well. Generally speaking, based on the degree of the MLC signal, a corresponding number of parallel paths operate in cooperation to decode the various levels of the MLC signal.

Abstract: A home wireless router establishes a Wireless Local Area Network (WLAN) that supports wireless communications within a WLAN service area. The home wireless router establishes broadband communications via a broadband connection with a VoIP service accumulator. The home wireless router services a plurality of wireless terminals within the WLAN service area, including at least one Voice over Internet Protocol (VoIP) wireless terminal. The home wireless router receives a query from the VoIP service accumulator requesting information regarding the home wireless router's prior servicing of (or ability to service) VoIP calls. In response, the home wireless router responds to the VoIP service accumulator with information regarding the home wireless router's prior servicing of (or ability to service) VoIP calls.

Abstract: Fast min*? (min-star-minus) or max*? (max-star-minus) circuit in LDPC (Low Density Parity Check) decoder. A novel and efficient approach by which certain of the calculations required to perform check node processing within various types of decoders is presented. The functionality and architectures presented herein are applicable to LDPC decoders and may also be employed within other types of decoders that are operable to decode other types of coded signals as well. The parallel and sometimes simultaneous calculation and determination of certain parts of the overall resultant of the max*? and/or min*? processing allows for very fast operation when compared to prior art approaches.

Abstract: LDPC (Low Density Parity Check) coded modulation hybrid decoding using non-Gray code maps for improved performance. Check node updating and symbol node updating are successively and alternatively performed on bit edge messages for a predetermined number of decoding iterations or until sufficient degree of precision is achieved. The symbol node updating of the bit edge messages uses symbol metrics corresponding to the symbol being decoded and the bit edge messages most recently updated by check node updating. The check node updating of the bit edge messages uses the bit edge messages most recently updated by symbol node updating. The symbol node updating computes possible soft symbol estimates. LDPC coded modulation hybrid decoding can decode an LDPC-BICM (Low Density Parity Check-Bit Interleaved Coded Modulation) signal having a symbol mapped using non-Gray code mapping. By using the non-Gray code mapping, a performance improvement is achieved over an only Gray code mapping system.

Abstract: Aspects of the invention provide a system for a mixed analog-digital automatic gain control. The received analog signal is amplified by the analog amplifier and then converted to a digital value by an ADC. A clamp reference level of the converted signal is removed prior to applying a digital gain to a digital multiplied. Once the digital gain is applied, the clamp reference level is restored to the digital signal. A loop filter determines the system time response from the error between an amplitude parameter of the received signal and an AGC reference level. A gain separation circuit generates the system gain and separates it into a digital gain and an analog gain in a way to maximize the use of the analog amplifier. The analog gain is applied to the analog amplifier and the digital gain is applied to the digital multiplier.

Abstract: Directly computing Feed Forward Equalizer (FFE) coefficients and Feed Back Equalizer (FBE) coefficients of a Decision Feedback Equalizer (DFE) from a channel estimate. The FBE coefficients have an energy constraint. A recursive least squares problem is formulated based upon the DFE configuration, the channel estimate, and the FBE energy constraint. The recursive least squares problem is solved to yield the FFE coefficients. The FFE coefficients are convolved with a convolution matrix that is based upon the channel estimate to yield the FBE coefficients. A solution to the recursive least squares problem is interpreted as a Kalman gain vector. A Kalman gain vector solution to the recursive least squares problem may be determined using a Fast Transversal Filter (FTF) algorithm.

Abstract: A system and method in which user management and radio management functionalities associated with a wireless network, such as an IEEE 802.11 wireless network, are integrated to provide wireless network services thereof. In general, according to the present invention disclosed herein, a link layer authentication module for linking a plurality of wireless network layers to one another is integrated with a network management module, such that the network management module and the link layer authentication module together form an integrated user and radio management module which provides wireless network services for the wireless network. The use of link layer authentication under the IEEE 802.1x standard can be integrated with network management functionality thereof in order to associate both and provide a variety of useful wireless network services.

Abstract: A high-speed serial demultiplexer receives over four high-speed serial data lines at a nominal rate of 10 GBPS and demultiplexes the data to 16 lines with a rate of 2.5 GHz each. The demultiplexer circuits are configured as two D type latches, one of which latches data on the positive edge of a 5 GHz clock, the other of which latches every other bit of the 10 GBPS data on the negative edge of the 5 GHz clock, alternating with the first D latch. Each of the two D latches is configured as a master-slave flip-flop that includes a master D latch and a slave D latch. The master receives the data at the 10 GBPS rate and clocks every other bit to its output using an edge of the 5 GHz clock (the positive edge for one of the D-latches, the negative for the other). The slave clocks the data form the master to its output on the opposite edge of the clock following the master.

Abstract: According to one exemplary embodiment, a synchronous power gauge is coupled to a processor for determining total charge consumed from a power source in an electronic device. The synchronous power gauge includes a controller for receiving a synch signal that indicates whether the electronic device is in an operating power mode or a low power mode. The synchronous power gauge further includes an analog to digital converter controlled by the controller and is configured to process a signal associated with current drawn from the power source when the electronic device is in the operating power mode. An accumulator coupled to the analog to digital converter maintains and updates a sum of digital outputs provided by the analog to digital converter when the electronic device is in the operating power mode. The processor uses the sum of digital outputs to determine the total charge consumed from the power source.

Abstract: A programmable antenna includes a fixed antenna element and a programmable antenna element that is tunable to one of a plurality of resonant frequencies in response to at least one antenna control signal. A programmable impedance matching network is tunable in response to at least one matching network control signal, to provide a substantially constant load impedance. A control module generates the antenna control signals and the matching network control signals, in response to a frequency selection signal.

Abstract: A cable modem includes a cable transceiver that provides bidirectional broadband access to a wide area network in accordance with a first wired communication protocol. A radio frequency (RF) transceiver provides bidirectional communication with a wireless telephone over a radio frequency link. A memory module stores a voice over internet protocol (VoIP) application. A processing module executes the VoIP application to provide VoIP service to the wireless telephone via the cable network.

Abstract: A RF receiver includes a low noise amplifier and blocking module, a down conversion module, and a local oscillation module. The low noise amplifier and blocking module is coupled to receive an inbound RF signal, wherein the amplified inbound RF signal includes a desired RF signal component and a blocking RF signal component; attenuate the blocking RF signal component of the amplified inbound RF signal; and pass, substantially unattenuated and amplified, the desired RF signal component of the inbound RF signal to produce a desired inbound RF signal. The down conversion module is coupled to convert desired inbound RF signal into an inbound signal based on a receive local oscillation. The local oscillation module is coupled to produce the receive local oscillation, wherein the local oscillation module includes a notch filter module coupled to attenuate signal components of the receive local oscillation at frequencies corresponding to harmonics of the blocking RF signal component.

Abstract: A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(l,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, error-tolerant sync mark detection, and the ability to recover data when the sync mark is obliterated allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery.

Abstract: The programmable slew rate driver uses separate and programmably selectable resistors for time constants for on and off transitions on the NMOS and PMOS output transistors. By proper setting of gate voltage time constants and overlap of NMOS and PMOS “on” times, a desired output slew rate is accomplished, having a smooth output transition, without generation of shoot-through current. The programmable slew rate driver includes a first driver transistor coupled between the first supply voltage and output, a second driver transistor coupled between the second supply voltage and output, a plurality of upper transition blocks coupled in parallel and a plurality of lower transition blocks coupled in parallel between the first and second supply voltage. The rates of change and overlap of the gate voltages are in turn substantially determined by the resistance of the lower transition control blocks and the capacitance of the gate of the second driver transistor.

Abstract: A processing device includes one or more resources, a plurality of peripheral bus interfaces that support resource sharing with a plurality of other processing devices, a primary routing resources and a node ID register. The primary routing resources are programmable with a plurality of address ranges. The processing device is operable to determine a routing of peripheral bus transactions among the plurality of peripheral bus interfaces based upon a destination address of the peripheral bus transaction and primary routing resources contents. The node ID register is programmable with a plurality of override indications. The processing device is operable to determine an override routing of peripheral bus transactions among the plurality of peripheral bus interfaces based upon a destination node ID of the peripheral bus transaction and node ID register contents.

Abstract: A Radio Frequency (RF) receiver includes a low noise amplifier (LNA) and a mixer coupled to the output of the LNA. The gain of the LNA is adjusted to maximize signal-to-noise ratio of the mixer and to force the mixer to operate well within its linear region when an intermodulation interference component is present. The RF receiver includes a first received signal strength indicator (RSSI_A) coupled to the output of the mixer that measures the strength of the wideband signal at that point. A second received signal strength indicator (RSSI_B) couples after the BPF and measures the strength of the narrowband signal. The LNA gain is set based upon these signal strengths. By altering the gain of the LNA by one step and measuring the difference between a prior RSSI_B reading and a subsequent RSSI_B? reading will indicate whether intermodulation interference is present.

Abstract: A wireless device and system employs a two-dimensional (2-D) Trellis code that can be applied to Quadrature Phase Shift Keying (QPSK) and higher order Quadrature Amplitude Modulation (QAM) constellations. The Trellis codes employed have optimal Euclidean distance properties for QPSK constellations, and have very good Euclidean distance properties for higher-order QAM constellations. The Trellis codes are suited for transmission systems that adopt multi-mode QPSK and QAM constellations with different data rates since the same Trellis code can be applied to all modulation formats and the same decoder can be used at the receiver for all modulation formats. Modulation formats include QPSK, 8-QAM, 16-QAM, 32-QAM, and 64-QAM and may be extended to even higher order modulations formats.

Abstract: A system, method, and apparatus for dynamically booting processor code memory with a wait instruction is presented herein. A wait instruction precedes the transfer of a new code portion to the code memory. The wait instruction causes the processor to temporarily cease using the code memory. When the processor ceases using the code memory, the processor signals a direct memory access (DMA) module to transfer a new code portion to the code memory. The DMA module transfers the new code portion to the code memory and transmits a signal to the processor when the transfer is completed. The signal causes the processor to resume. When the processor resumes, the processor begins executing the instructions at the next code address.

Abstract: A method and apparatus for performing trellis coded modulation of signals for transmission on a TDMA channel of a cable network, such as a DOCSIS cable network, is provided. In an embodiment, an upstream modulator portion of a cable modem receives burst data, selectively encodes the burst data for trellis coded modulation to generate encoded symbols, and modulates the encoded symbols for selective transmission over a time division multiple access (TDMA) channel or a synchronous code division multiple access (S-CDMA) channel of the cable network.

Abstract: A system and method is presented to utilize hardware instead of software to compare for bandwidth request changes between two consecutively received unsolicited grant service (UGS) extended headers for the same service identifier (SID), obtains significant savings in CPU cycles for the CMTS software. The system determines whether adequate bandwidth is being provided from a cable modem termination system to a data provider during a unsolicited grant service flow. The system includes a means for receiving a current voice packet in the unsolicited grant service flow at the cable modem termination system from the data provider, where the current voice packet comprises a unsolicited grant service extended header. The system further includes means for comparing the current unsolicited grant service extended header with a previous unsolicited grant service extended header.