Patents Assigned to Broadcom Corporation
  • Publication number: 20030176161
    Abstract: A downstream adaptive modulation system and method. The downstream adaptive modulation system comprises a wireless access termination system and one or more wireless modems. The wireless access termination system includes a plurality of queues and a parser. The parser parses data traffic onto the plurality of queues. Each queue is associated with a different coding and modulation scheme. Each of the one or more wireless modems receives data traffic from the plurality of queues based on the wireless modem's ability to demodulate and decode the signal from each of the plurality of queues. When a wireless modem experiences a change in signal strength, the present invention enables the wireless modem to adapt to data from other queues to compensate for the change in signal strength. Thus, if the signal strength improves over a period of time, the wireless modem may receive data at a higher order modulation and FEC code rate.
    Type: Application
    Filed: March 15, 2002
    Publication date: September 18, 2003
    Applicant: Broadcom Corporation
    Inventors: Mark Dale, David Hartman, Anders Hebsgaard
  • Publication number: 20030174705
    Abstract: A process of filtering packet data in a network device is disclosed. A descriptor table is accessed to obtain a first descriptor and a first field is extracted from a packet based on the first descriptor. An action table is accessed based on a value of the first field of the packet. Then an action from the action table is executed when a valid bit from the action table for the action is set or an action from a miss action table is executed when a valid bit from the action table for the action is not set.
    Type: Application
    Filed: September 5, 2002
    Publication date: September 18, 2003
    Applicant: Broadcom Corporation
    Inventors: Laxman Shankar, Shekhar Ambe
  • Publication number: 20030174706
    Abstract: A network device includes a port, a mapping module, a signaling module, an encapsulation module, a port interface, and an address learning module. The port is configured to send and receive a packet. The mapping module is configured to determine a virtual path LAN segment assigned to the port. The signaling module is configured to determine virtual channel information assigned to the port. The signaling module is configured to exchange the virtual channel information to a second network entity. The encapsulation module is configured to add stacking labels to a header of the packet. The encapsulation module is configured to assign a quality of service to be applied to the packet. The port interface is configured to map a routing path for the packet. The address learning module is configured to learn the routing path to transport the packet from the first to the second network entity.
    Type: Application
    Filed: March 4, 2003
    Publication date: September 18, 2003
    Applicant: Broadcom Corporation
    Inventors: Laxman Shankar, Shekhar Ambe
  • Publication number: 20030177257
    Abstract: A network component for processing a packet includes at least one first storage unit, at least one second storage unit, at least one third storage unit, and an action implementation unit. The at least one first storage unit is configured to store an initial bit value selected from within the packet. The at least one second storage unit is configured to store a bit action length value. The at least one third storage unit is configured to store an extracted bit value based upon the initial bit value and the bit action length value. The action implementation unit is configured to implement at least one action on a packet by using an action bit value to modify the extracted bit value.
    Type: Application
    Filed: December 12, 2002
    Publication date: September 18, 2003
    Applicant: Broadcom Corporation
    Inventor: Sandeep Relan
  • Publication number: 20030177002
    Abstract: A method of determining a pitch period of an audio signal using a correlation-based signal derived from the audio signal. The correlation-based signal includes known peaks each corresponding to a respective one of known time lags. The known peaks includes a global maximum peak. The method comprises: (a) determining if a candidate peak among the local peaks exceeds a peak threshold; (b) determining if a candidate time lag corresponding to the candidate peak is within a predetermined range of at least one integer sub-multiple of the time lag corresponding to the global maximum peak; and (c) setting the pitch period equal to the candidate time lag when the determinations of both steps (a) and (b) are true.
    Type: Application
    Filed: October 31, 2002
    Publication date: September 18, 2003
    Applicant: Broadcom Corporation
    Inventor: Juin-Hwey Chen
  • Patent number: 6621675
    Abstract: A voltage regulator may include one or more features for generating high PSRR. For example, source follower devices may be included in the voltage regulator for providing current sources for the output voltage nodes. The source followers may be sensitive to power supply noise at the gate terminal. Filters are included on the gate terminals to filter the power supply noise, thus reducing the noise at the gate terminals. As another example, the voltage regulator may employ current sources on the output voltage nodes which produce current inversely proportional to the current drawn by the load. In one embodiment, the voltage regulator may include a power control circuit used to provide overvoltage protection during power up. The power control circuit provides a voltage during power up, and ceases providing the voltage after a time interval so that the circuit may operate.
    Type: Grant
    Filed: April 11, 2001
    Date of Patent: September 16, 2003
    Assignee: Broadcom Corporation
    Inventor: Joseph M. Ingino, Jr.
  • Patent number: 6621362
    Abstract: Method and circuitry for implementing VCOs with improved frequency band switching use differentially-coupled varactors to implement the different frequency bands. According to a specific embodiment, one side of a varactor couples to the tank circuit and the other side is coupled either to ground or to the positive power supply VDD without introducing any series parasitic resistance.
    Type: Grant
    Filed: May 18, 2001
    Date of Patent: September 16, 2003
    Assignee: Broadcom Corporation
    Inventors: Afshin Momtaz, Armond Hairapetian
  • Patent number: 6621350
    Abstract: There is provided a circuit and method for providing a supply voltage to an operational amplifier. A switch has a plurality of inputs connected to a respective plurality of supply voltages. An output of the switch is connected to a supply voltage terminal of an operational amplifier. The input of the switch is selected in dependence of the voltage levels to which a signal is to be amplified.
    Type: Grant
    Filed: March 12, 2002
    Date of Patent: September 16, 2003
    Assignee: Broadcom Corporation
    Inventors: Rudi Verbist, Raphael Cassiers
  • Publication number: 20030169827
    Abstract: A self-calibrating transmitter includes an up-conversion mixing module, summing module, calibration determination module, and a calibration execution module. The up-conversion mixing module is operably coupled to mix an I component of a base-band signal with an I component of a local oscillation to produce a mixed I signal and is also operably coupled to mix a Q component of the base-band signal with a Q component of the local oscillation to produce a mixed Q signal. The summing module sums the mixed I signal with the mixed Q signal to produce a modulated radio frequency (RF) signal. The calibration determination module is operably coupled to produce a calibration signal, which it generates by interpreting the local oscillation and the modulated RF signal. The calibration execution module is operably coupled to calibrate the DC level of the I and/or Q component of the base-band signal, and/or the gain of the I and/or Q component of the base-band signal based on the calibration signal.
    Type: Application
    Filed: March 8, 2002
    Publication date: September 11, 2003
    Applicant: Broadcom Corporation
    Inventors: Hong Shi, Henrik T. Jensen
  • Publication number: 20030172220
    Abstract: The present invention provides a method of controlling data flow within a network device. The method includes the steps of snooping a data packet before the data packet is stored in a memory buffer of the network device to determine a packet size, aggregating the packet size to generate a total number of data packets within a burst if the packet size exceeds a predetermined packet size. The method also includes the steps of lowering a threshold of the memory buffer to a reset threshold if the total number of data packets exceeds a predetermined number of consecutive data packets and activating a pause frame based upon the reset threshold to temporarily suspend transmission of incoming data packets to the network device.
    Type: Application
    Filed: March 6, 2002
    Publication date: September 11, 2003
    Applicant: Broadcom Corporation
    Inventor: Yi-Hsien Hao
  • Publication number: 20030169735
    Abstract: A method, apparatus and computer program product is provided for classifying a target data packet entering a network interface. For each of a plurality of received classification parameters, at least one program module is generated. Each program module tests a pre-defined field(s) of the target data packet for adherence to the classification parameter(s) with which the program module is associated. A pre-classification header is generated wherein an indication is made of where one or more pre-defined fields are located in the data packet if the field is present. Maintaining locations of the pre-defined fields of the target data packet in the pre-classification header prevents having to recalculate the addresses of the pre-defined fields of the target data packet. Eliminating the need for re-calculating the addresses of the pre-defined field(s) can allow the classification process of the present invention to obtain an optimal execution speed.
    Type: Application
    Filed: March 5, 2002
    Publication date: September 11, 2003
    Applicant: Broadcom Corporation
    Inventors: Thomas L. Johnson, Joel Danzig, Paul Burrell
  • Publication number: 20030172183
    Abstract: A system, method and computer program product is provided for caching domain name system (DNS) information on a network gateway. In particular, a network gateway that interfaces one or more customer premises equipment (CPE) devices to an IP network maintains a centralized on-board cache for storing domain names and corresponding IP addresses. The domain names and IP addresses in the cache are used by the network gateway to resolve DNS queries generated by application programs running on the CPE devices in a manner that is transparent to the CPE devices and that does not expend CPE resources. The cache may be initially loaded by an attached CPE or an external network entity and is continuously populated with information extracted from DNS messages exchanged between a CPE device and the external IP network.
    Type: Application
    Filed: February 25, 2002
    Publication date: September 11, 2003
    Applicant: Broadcom Corporation
    Inventors: Charles Edward Anderson, Thomas Carroll Willis, Jason Andrew Willis
  • Publication number: 20030169686
    Abstract: The present invention provides for handling data flow within a network device, which includes a cycle timing module, a division module, an assignment module, and an input device. The cycle timing module is configured to determine the cycle time needed to process a set of incoming data. The division module is configured to divide a serial shifting bus into a plurality of segments, wherein the serial shifting bus is included within the network to transfer the data. The assignment module is configured to assign a plurality of assembly lines to each segment, wherein each of the assembly lines is connected to the serial shifting bus. The serial shifting bus serially shifting the data until the data reaches end of the bus segment. The end of the serial bus segment is configured to transfer the data out of the serial shifting bus to a management information base processing unit.
    Type: Application
    Filed: March 6, 2002
    Publication date: September 11, 2003
    Applicant: Broadcom Corporation
    Inventor: Shih-Hsiung Ni
  • Patent number: 6618302
    Abstract: A single-port hierarchical memory structure including memory modules having memory cells; hierarchically-coupled local and global sense amplifiers; hierarchically-coupled local and global row decoders; and a predecoding circuit coupled with selected global row decoders. The predecoding circuit is disposed to provide predecoding at a speed substantially faster than the predetermined memory access speed of the memory structure, allowing access to a memory cell at least twice during the memory access period, thereby providing dual-port functionality. A WRITE-AFTER-READ operation without a separate, interposed PRECHARGE cycle, is completed within one memory access cycle of the hierarchical memory structure. The method includes locally selecting the first memory location of a first datum; locally sensing the first datum (i.e.
    Type: Grant
    Filed: June 18, 2002
    Date of Patent: September 9, 2003
    Assignee: Broadcom Corporation
    Inventors: Esin Terzioglu, Morteza Cyrus Afghahi
  • Patent number: 6618440
    Abstract: An image data decompression apparatus for decoding blocks of motion compensated non-intra coded data uses a memory (14) storing reference picture data. A decoding processor (12) decodes a current block of a generated picture using lines of previously decoded image data from the memory (14) that are selected in dependence upon a motion vector (V1) for the current block. In order to improve access efficiency to the memory (14) the decoding processor (12) concatenates fetches into bursts for different sections of lines of previously decoded data that lie within a predetermined range within the memory addresses of the memory (14).
    Type: Grant
    Filed: November 12, 1999
    Date of Patent: September 9, 2003
    Assignee: Broadcom Corporation
    Inventor: Mark Taunton
  • Publication number: 20030164743
    Abstract: A varactor folding technique reduces noise in controllable electronic oscillators through the use of a series of varactors having relatively small capacitance. A folding circuit provides control signals to the varactors in a sequential manner to provide a relatively smooth change in the total capacitance of the oscillator. Consequently, effective control of the oscillator is achieved with accompanying reductions in oscillator noise such as flicker noise.
    Type: Application
    Filed: March 25, 2003
    Publication date: September 4, 2003
    Applicant: Broadcom Corporation
    Inventors: Ramon Alejandro Gomez, Lawrence M. Burns, Alexandre Kral
  • Publication number: 20030164725
    Abstract: An input circuit has hysteresis to mitigate the effects of input noise. The input circuit receives an analog input signal and determines whether the unregulated analog input signal is a high or a low voltage. The input circuit outputs a regulated low voltage (i.e., “0”) for a low input signal, and outputs a regulated high voltage (i.e., “1”) for a high input signal. The low-to-high transition occurs at a higher voltage than a high-to-low transition, which mitigates noise on the input signal. Furthermore, the comparator includes a feedback path from an output of the comparator to an input of the comparator. The feedback path causes some delay in any output voltage transition (i.e. high-to-low output transition or low-to-high transition), which further enhances the hystersis effect and improves noise immunity. An embodiment of the circuit interfaces with high voltage (e.g., 5V) input signals and outputs low voltage (e.g., 1.2V) output signals.
    Type: Application
    Filed: September 27, 2002
    Publication date: September 4, 2003
    Applicant: Broadcom Corporation
    Inventor: Janardhanan S. Ajit
  • Publication number: 20030164722
    Abstract: A system and method for compensating for process, voltage, and temperature variations in a circuit is provided. A system includes an inverter having an input port, and an output port, and is configured to (i) receive an input signal, (ii) delay the received input signal, and (iii) provide the delayed signal to the inverter output port. The system also includes a logic device including at least two input ports and an output port. A first of the at least two input ports is configured to receive the delayed signal. Finally, the system includes a charge storing device having a first end coupled, at least indirectly, to a second of the at least two input ports and a second end coupled to a logic device common node. The charge storing device is configured to (i) receive the input signal and (ii) sense a rate of change in voltage of the received input signal, the sensed voltage being representative of a corresponding current.
    Type: Application
    Filed: November 14, 2002
    Publication date: September 4, 2003
    Applicant: Broadcom Corporation
    Inventor: Janardhanan S. Ajit
  • Publication number: 20030165209
    Abstract: A phase lock loop frequency synthesizer includes a phase rotator in the feedback path of the PLL. The PLL includes a phase detector, a low pass filter, a charge pump, a voltage controlled oscillator (“VCO”), and a feed back path connecting output of the VCO to the phase detector. The feedback path includes a phase rotator connected to the output of the VCO and to an input of a frequency divider. Coarse frequency control is implemented by adjusting the input reference frequency to the phase detector or by adjusting the divider ratio of the frequency divider. Fine frequency control is achieved by increasing or decreasing the rotation speed of the phase rotator. The phase rotator constantly rotates phase of the VCO output, thereby causing a frequency shift at the output of the phase rotator. The rotation speed of the phase rotator is controlled by an accumulator and a digital frequency control word.
    Type: Application
    Filed: October 31, 2002
    Publication date: September 4, 2003
    Applicant: Broadcom Corporation
    Inventors: Chun-Ying Chen, Michael Q. Le, Myles Wakayama
  • Patent number: 6614371
    Abstract: In accordance with the present invention a data processing circuit includes a first data path for processing first data. The first data path includes a first data storage circuit. A second data path is provided for processing second data. The second data path includes a second data storage circuit. A multiplexer having a first input coupled to the first data path and a second input coupled to the second data path receives the stored values. The multiplexer includes a select input coupled to a clock signal. A delay circuit is configured to delay storage of the second data in the second data storage circuit, wherein the first data storage circuit stores the first data in response to receiving a first timing signal, and the second data storage circuit stores the second data in response to receiving a second timing signal.
    Type: Grant
    Filed: July 19, 2001
    Date of Patent: September 2, 2003
    Assignee: Broadcom Corporation
    Inventor: Bo Zhang