Abstract: An integrated receiver with channel selection and image rejection is substantially implemented on a single CMOS integrated circuit. A receiver front end provides programable attenuation and a programable gain low noise amplifier. LC filters integrated onto the substrate in conjunction with image reject mixers provide image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. Active filters utilize multi track spiral inductors with shields to increase circuit Q. Frequency planning provides additional image rejection. Local oscillator signal generation methods on chip reduce distortion. A PLL generates needed out of band LO signals. Direct synthesis generates in band LO signals. PLL VCOs are centered automatically. A differential crystal oscillator provides a frequency reference. Differential signal transmission throughout the receiver is used. ESD protection is provided by a pad ring and ESD clamping structure.

Abstract: Provided is an architecture for a cryptography accelerator chip that allows significant performance improvements over previous prior art designs. In various embodiments, the architecture enables parallel processing of packets through a plurality of cryptography engines and includes a classification engine configured to efficiently process encryption/decryption of data packets. Cryptography acceleration chips in accordance may be incorporated on network line cards or service modules and used in applications as diverse as connecting a single computer to a WAN, to large corporate networks, to networks servicing wide geographic areas (e.g., cities). The present invention provides improved performance over the prior art designs, with much reduced local memory requirements, in some cases requiring no additional external memory. In some embodiments, the present invention enables sustained full duplex Gigabit rate security processing of IPSec protocol data packets.

Abstract: A method for establishing a virtual channel between network devices is disclosed. In the case of a local network device establishing a virtual channel with a remote network device, a virtual channel request message is sent from the local network device to the remote network device. A virtual channel acknowledgement message and a remote capability list are received and a virtual channel resume message and a local capability list are sent. The virtual channel is then enabled. In the case of a remote network device establishing a virtual channel with a local network device, a virtual channel request message is received from a local network device by a remote network device. A virtual channel acknowledgement message and a remote capability list are sent and a virtual channel resume message and a local capability list are received. The virtual channel is then enabled.

Abstract: The method and system of the present invention superimposes read and write operations by connecting the global bit lines that are not selected to the Vdd. As a result, the respective local sense amplifiers for the non-selected global bit lines will just read and refresh the respective memory cells. This new approach results in smaller local sense amplifiers and one global sense amplifiers for several memory cells (and local sense amplifiers).

Abstract: An extended range variable gain amplifier is described. The variable gain capability is achieved by replacing differential pair amplifiers having an input signal with less attenuation with one having an input signal that is more attenuated. This replacement continues until only ten differential pair amplifiers are remaining. At this point, if less gain is desired, differential pair amplifiers are turned off, but are not replaced. A minimum number of amplifiers will remain on.

Abstract: A method for selectively controlling the flow of data through a network device is discussed. The network device has a plurality of ports, with each port of the plurality of ports having a plurality of priority queues. Congestion at one priority queue of the plurality of priority queues is detected and a virtual channel message is sent to other network devices connected to the network device causing data destined for the one priority queue to be halted. After the congestion at the one priority queue has abated, a virtual channel resume message is sent to the other network devices.

Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

Abstract: Continuously tuning a transconductance. Coupling a degeneration resistance from a first source of a first transistor in a differential pair of transistors to a second source of a second transistor in the differential pair of transistors. Applying a second variable degeneration resistance in parallel to the first degeneration resistance in response to the application of a first variable control voltage. And applying a third variable degeneration resistance in parallel to the first degeneration resistance and the second degeneration resistance in response to the application of a second variable control voltage having a fixed voltage offset from the first variable control voltage.

Abstract: A method and system for providing antialiasing of a graphical image on a display from data describing at least one object is disclosed. The display includes a plurality of pixels. The method and system include providing a plurality of fragments for the at least one object. A portion of the plurality of fragments intersects a pixel of the plurality of pixels. Each of the plurality of fragments includes a depth value, a slope of the depth value, and an indication of a portion of a corresponding pixel that is intersected. The method and system include calculating a plurality of subpixel depth values for a fragment of the plurality of fragments. The plurality of subpixel depth values is calculated using the depth value and the slope of the depth value of the fragment. The method and system include determining whether to store a portion of the fragment based on the plurality of subpixel depth values for the fragment and the indication of the extent the corresponding pixel is intersected by the fragment.

Abstract: Provided is an architecture for a cryptography accelerator chip that allows significant performance improvements over previous prior art designs. In various embodiments, the architecture enables parallel processing of packets through a plurality of cryptography engines and includes a classification engine configured to efficiently process encryption/decryption of data packets. Cryptography acceleration chips in accordance may be incorporated on network line cards or service modules and used in applications as diverse as connecting a single computer to a WAN, to large corporate networks, to networks servicing wide geographic areas (e.g., cities). The present invention provides improved performance over the prior art designs, with much reduced local memory requirements, in some cases requiring no additional external memory. In some embodiments, the present invention enables sustained full duplex Gigabit rate security processing of IPSec protocol data packets.

Abstract: The invention provides apparatus and a method of scan testing digital logic circuits, in particular faults in circuit operation during operational transitions in the circuit. The system is intended for use in testing a logic circuit which is driven by high frequency oscillating means and an external clock, which external clock during normal operation is used to time control of the operation of the circuit; system disabling the external clock, synchronising testing means with the internal oscillating means, performing testing on the circuit while the external clock is disabled and re-enabling the external clock following testing. In the preferred embodiment, the test clock is synchronised with a PLL. The preferred embodiments address the difficulties with the conventional test methodology by synchronising the test clock with the phase locked loop internal to the IC.

Abstract: A system and method for management of bandwidth in a fiber optic, ethernet-based, TDMA communications system. A request/grant process is used to control the use of upstream bandwidth. A sense of time must therefore be shared by a headend and remote end-user devices. The invention provides for a gigabit media-independent interface in a media access controller to detect start-of-frame delimiters in incoming data. This allows for synchronization of a headend and end-user devices. The invention also allows for phase locking a transmit bit rate, at a headend, to the headend's clock. Transmitted data can the be used downstream to derive a local clock. Synchronization can also be maintained by the use of synchronization bytes in MPEG frames and/or variable length frames. Efficient bandwidth usage can also be facilitated by the use of maximum data units in allocating bandwidth in unsolicited grants, and by allowing flexible fragmentation and/or prioritization of internet protocol (IP) packets.

Abstract: A system, method, and computer program product for management of bandwidth, quality of service, and operational efficiency with respect to delivery of video in a fiber optic, ethernet-based, TDMA communications system. An optical node is placed between a hub and the user, and functionality is placed at the optical node to facilitate the provision of user services. The invention allows improved access to video by buffering a sequence of frames at the optical node. When a user accesses a channel part way through a transmission, a group of pictures starting with the initial frame will be available, and no frames will have been missed. Moreover, the function of responding to a user's command to switch channels is placed at the optical node, instead of at a more distant hub. This improves responsiveness to such commands. Also, when a user repeatedly attempts to access different sequences of frames (“channel surfing”), the optical node will detect such repeated access.

Abstract: A fiber optic, ethernet-based, TDMA communications system that addresses issues of cost, quality of service, and operational efficiency. An aggregating optical node is placed between a hub and end users. This allows the use of less expensive lasers, and permits a variety of connection topologies (e.g., fast ethernet point-to-point, shared broadcast, and gigabit ethernet) between the optical node and the end users. The use of an optical node also allows allocation of certain functions (e.g., bandwidth allocation) to the optical node. Moreover, an adaptive equalizer can be used in conjunction with any laser in the system to improve its signal to noise ratio.

Abstract: A system for management of bandwidth, cost control, and operational efficiency in a fiber optic, ethernet-based, TDMA communications system. The invention features an aggregating optical node between a central office and end users. The optical spectrum is divided according to end user, direction (i.e., upstream or downstream), and/or according to function (e.g., video or non-video). In an embodiment of the invention, a wavelength coupler can be used to couple multiple upstream wavelengths from respective end-user devices, for forwarding to a central office. Moreover, adaptive equalization can be used for noise cancellation purposes.

Abstract: A compensation circuit compensates for the variation in the internal resistance of a multi-track inductor over temperature. The compensation circuit includes a dummy inductor that has the same temperature dependent resistance as that of the multi-track inductor that is to be compensated. A first field effect transistor is placed in series with the multi-track inductor that is to be compensated, and a second field effect transistor is placed in series with the dummy inductor, where the gates of the FETs are tied together. A control circuit provides a constant current for the dummy inductor and detects any changes in voltage of the dummy inductor over temperature. The control circuit includes a feedback loop that controls the gate voltage of both first and second FETs so as to compensate for the temperature dependent inductor resistance variations of both the dummy inductor and the multi-track inductor that is to be compensated.

Abstract: A method and apparatus to ensure DLL locking at a minimum delay is provided. In one embodiment, a DLL circuit includes a phase detector, a counter, a programmable delay line, and a counter control circuit. Upon initialization of the DLL circuit, the counter control circuit is configured to cause the counter to count increment, regardless of the phase relationship between a reference clock signal and the output clock signal. The counter continues incrementing, thereby changing the phase relationship between the reference clock signal and the output clock signal by adjusting the delay of the programmable delay line. This eventually results in a phase lock between the reference clock signal and the output clock signal at a minimum delay. Once the DLL achieves a phase lock between the reference clock signal and the output clock signal, the counter increments or decrements its count in order to maintain or re-acquire a lock.

Abstract: A signal processing system which discriminates between voice signals and data signals modulated by a voiceband carrier. The signal processing system includes a voice exchange, a data exchange and a call discriminator. The voice exchange is capable of exchanging voice signals between a switched circuit network and a packet based network. The signal processing system also includes a data exchange capable of exchanging data signals modulated by a voiceband carrier on the switched circuit network with unmodulated data signal packets on the packet based network. The data exchange is performed by demodulating data signals from the switched circuit network for transmission on the packet based network, and modulating data signal packets from the packet based network for transmission on the switched circuit network. The call discriminator is used to selectively enable the voice exchange and data exchange.

Abstract: First and second address-selection information, as well as first and second read/write information, is contemporaneously provided to various enabling circuits. The enabling circuits can then enable one or more first memory cells based on the first address-selection and first read/write information, and further enable the one or more second memory cells based on the second address-selection information and read/write information. Data can then be written to, or read from, the enabled memory cells in a single memory-access cycle.

Abstract: An address device simultaneously provides a first address to a first memory section using a first address bus and a second, incrementally higher, address to a second memory section using a second address bus. A buffer can then read from or write to the first and second memory sections. During a read operation, the buffer can receive a first portion of a misaligned data word from the first memory section and read a second portion of the misaligned data word from the second memory section and assemble the data in the data word from the first and second portions. When the access operation is a write operation, the buffer can effectively perform a shift operation on the data in the data word, then write a first portion of the word to the first memory section and write a second portion of the word to the second memory section. Accordingly, data accesses that would take two memory-access cycles on a conventional memory system are reduced to a single memory-access cycle.