Abstract: A computer system for conditionally performing an operation defined in a computer instruction, an execution unit of the computer system comprises at least one operand store for holding operands on which an operation defined in an instruction is to be performed, wherein said operand store defines a plurality of lanes each holding an object, a plurality of operators associated respectively with the lanes for carrying out an operation specified in an instruction on objects in the operand lanes, a destination store for holding objects resulting from the operation on a lane by lane basis, a plurality of control stores each comprising a plurality of indicators to control for each lane whether or not an operation defined in an instruction is to be performed on that lane, and control circuitry for controlling which of said plurality of control stores is to be used to control per lane execution of an instruction, the control circuitry being operative to select a control store from the plurality of control stores based

Abstract: System for measuring a thickness of a circuit component on a printed circuit board (PCB). The system includes a first circuit, a power plane, a power strip, a calibration strip, a temperature sensor, and a second circuit. The power plane is coupled to the first circuit. The power strip is for providing power to the power plane and is disposed in the PCB connected to the power plane. The power strip has at least two vias. The calibration strip has a predetermined width and is disposed in said PCB. The calibration strip has at least two vias for measuring a voltage drop. The temperature sensor is coupled to the calibration strip and configured to measuring a temperature of the calibration strip. The second circuit is coupled to the temperature sensor and configured to determine the thickness of the calibration strip based on at least the temperature of the calibration strip.

Abstract: A system, method and computer program product is provided for mitigating the effects of burst noise on packets transmitted in a communications system, wherein each packet includes two or more FEC blocks. A receiving device implements an FEC block reconstruction technique to restore FEC blocks that have been corrupted by burst noise. In accordance with this technique, the receiving device receives some but not all of the FEC blocks of a transmitted packet. The receiving device then replaces the bad FEC blocks with good FEC blocks from a repeated packet transmission, if repetition outer coding is used, or by requesting retransmission of the bad FEC blocks or the entire original packet from a transmitting device, if a retransmission technique is used. A combination of repetition coding, retransmission, and FEC block reconstruction may also be used.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: A system and method for converting an analog input signal to a N-bit digital output signal. The invention comprises generating a plurality of reference voltage signals; pre-amplifying, separately, a difference between each of the plurality of reference voltage signals and an analog input signal using a plurality of cascaded, differential, switched-capacitor circuits to output a plurality of pre-amplified difference signals; and determining a zero-crossing result for each of the plurality of pre-amplified difference signals. Then one of a binary 1 and a binary 0 are assigned to each of the compared, pre-amplified signals. The binary 1's and 0's are encoded as an M-bit encoded signal, which is then decoded to output an N-bit digital output signal, wherein M is less that or equal to N.

Abstract: Various systems and methods providing signal delay compensation for circuits such as a multi-pair gigabit Ethernet transceiver are disclosed. In an analog implementation a buffer with an adjustable delay may be used to minimize the delay mismatch between clock trees. The delay of the adjustable-delay buffer is controlled by bias voltages that determine the charging and discharging current to the adjustable buffer. A phase detector circuit is used to compare the clock phases for rising and falling edges, and to adjust the bias voltages that control these edges. In a digital implementation a selector switch, responsive to a phase detector, may be used to route clock signals through circuit elements to delay clock signals.

Abstract: A current source DAC has calibration of the current sources used for providing the analog output. There are two outputs, one of which provides the output current or else a differential output is provided. The calibration is cyclic and the current source outputs switched to the output terminals are selected as a function of the point within the calibration cycle. The current stage of the cyclic calibration process is thus taken into account in the D/A conversion. For example, the average time since calibration for all current sources having outputs switched to the first output may be approximately equal to the average time since calibration for all current sources having outputs switched to the second output. In this way, the average current of the cells switched to one terminal is identical to the average current of the cells switched to the other terminal, and the average current of the cells switched to each terminal remains constant in time irrespective of the digital signal value being converted.

Abstract: A graphics display system integrated circuit processes analog video input, digital video input, and graphics input. The system incorporates a graphics accelerator that includes memory for graphics data. The accelerator preferably includes a coprocessor for performing vector type operations on a plurality of components of one pixel of the graphics data. The accelerator also includes an expanded instruction set for storing and loading data.

Abstract: A method of conditionally executing branch instructions which comprise an opcode field defining a type of test to be applied to determine whether or not to execute a branch operation, a control field designating a control store holding a plurality of indicators and a destination field holding information on a branch target address. The method comprises determining from the opcode field whether or not the test will check the state of one indicator or a plurality of indicators in the designated control store, accessing the designated control store to check the state of said one or said plurality of indicators depending on the determination, and generating a branch target address using information in the destination field in dependence on the state of the or each indicator checked.

Abstract: An architecture and a method for a cryptography acceleration is disclosed that allows significant performance improvements without the use of external memory. Specifically, the chip architecture enables “cell-based” processing of random-length IP packets. The IP packets, which may be of variable and unknown size, are split into fixed-size “cells.” The fixed-sized cells are then processed and reassembled into packets. The cell-based packet processing architecture of the present invention allows the implementation of a processing pipeline that has known processing throughput and timing characteristics, thus making it possible to fetch and process the cells in a predictable time frame. The architecture is scalable and is also independent of the type of cryptography performed. The cells may be fetched ahead of time (pre-fetched) and the pipeline may be staged in such a manner that attached (local) memory is not required to store packet data or control parameters.

Abstract: An M-bit folding/interpolating analog-to-digital converter (ADC) circuit, comprising a reference voltage generator, a converter, an interpolator, an amplifying stage, a comparator, and an encoder. The converter has an amplifier that receives at least one of a plurality of first reference voltage signals and outputs a plurality of coarse bits. The converter also has N-number of folding blocks, which output a plurality of folded signals. Each folding block comprises a plurality of capacitors, a differential amplifier and a feedback element. The folded signals output by the converter are then interpolated, amplified, compared and output as a plurality of fine bits. The encoder receives the coarse and fine bits and outputs the digital signal.

Abstract: A method for setting indicators in a control store of a computer system for conditionally performing operations, comprises providing a control store setting instruction defining an execution condition and specifying a control store to be set according to the condition, specifying in the instruction an operand lane size over which a setting operation is to be performed, the operand lane size specified being selected from a plurality of predetermined operand lane sizes, performing the setting operation defined in the setting instruction on a per operand lane basis over a plurality of operand lanes, writing the result of the setting operation to the control store specified in the instruction to set a plurality of indicators on a lane by lane basis, wherein one or a predetermined plurality of indicators is set for each operand lane in dependence on the size of the operand lane defined in the instruction. An instruction for performing the preferred method is also disclosed.

Abstract: Method and apparatus for determining the stopping point of an iterative decoding process. In one embodiment the estimated values of an iteration of an iterative decoder are provided to a signature circuit. If the signature does not differ from the previous signature developed from a prior iteration, or the signature developed from an iteration prior to the previous iteration, the decoding stops. The variance may also be tested and compared to a threshold as a criteria to stop the iterative decoding.

Abstract: Digital data signals at a variable input frequency are converted by a numerically controlled oscillator and an interpolator to a signal at a fixed output sampling frequency. The conversion of the variable input frequency to the fixed output sampling frequency may be by a factor other than an integer. The interpolated digital data signals at the fixed output sampling frequency are then modulated into a pair of trigonometric signals at a programmable carrier frequency, one signal having a cosine function and the other signal having a sine function. The modulated signals at the fixed output sampling frequency are then combined to create a modulated signal at a carrier frequency determined by the frequency of the sine and cosine signals. The modulated signal is sampled at the fixed output sampling frequency and converted to a corresponding analog signal using a digital-to-analog converter.

Abstract: The present invention provides a system and method for performing ranging operations in a cable modem system. In accordance with embodiments of the present invention, transmission times, transmission power levels, transmission carrier frequencies, and pre-equalization parameters are adjusted to provide for robust operation of the cable modem system. More particularly, iterative processing steps are used to provide coefficient ordering, scaling, and aligning between the multiple cable modems and the cable modem termination system present in a cable modem system.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems. The C3MOS structure enables the use of a power supply voltage that may be larger than the voltage required by the CMOS fabrication process, further enhancing the performance of the circuit.

Abstract: An integrated circuit formed on a semiconductor chip, comprising a low pass filter circuit having a first resistor of a first resistance value and a capacitor of a first capacitance value, wherein the first resistance value and the first capacitance value determine a comer frequency of the filter; and a tuning circuit having a second resistor of a second resistance value, a switched-capacitor of a third resistance value and a comparator that compares two voltage signals to produce a control signal, wherein the control signal adjusts the first and second resistance values as a function of the third resistance value. The corner frequency of the filter can be adjusted by varying one or more reference voltage signals. In combination, the comer frequency of the filter is adjusted by changing the frequency of a clock that controls the switched-capacitor to decrease the circuit sensitivity.

Abstract: A system and method of creating a highly efficient digital amplifier which can take either analog or digital inputs, and produce a high power accurate representation of the input to drive speakers or other low impedance load is described. The system employs a transition detector and delay unit which allows the comparator of the signal modulator to ignore its inputs for a pre-determined number of subsequent clock cycles once an output transition has been detected. Through the use of faster clocks and variable clock cycle skips upon the comparator's output transition, finer resolution of the feedback's clock period for noise-shaping purposes is achieved. Finer resolution of the clock period allows the present invention to employ a more aggressive noise-shaping than previously possible.

Abstract: A method and apparatus for providing local control of processing elements in a network of multiple context processing element are provided. A multiple context processing element is configured to store a number of configuration memory contexts. This multiple context processing element maintains data of a current configuration. State information is received from at least one other multiple context processing element. At least one configuration control signal is generated in responses to the state information and the data of a current configuration. One of multiple configuration memory contexts is selected in response to the configuration control signal, the selected configuration memory context controlling the multiple context processing element. Each multiple context processing element in the networked array of multiple context processing elements has an assigned physical and virtual identification.

Abstract: A system and method is provided for interleaving data in a communication device. The system includes a memory that stores blocks of data to be interleaved. In addition to the memory, the system includes a write module and a read module, each of which is coupled to the memory. The write module is configured to receive a burst of data and write blocks of data from the burst into the memory. The write module is also configured to provide control information to the read logic. The control information includes a rolling burst counter and a burst profile bank identifier for each block. If interleaving is activated, the control information also includes information pertaining to how the read module should interleave the block. If interleaving is not activated, the control information also includes the byte length size of the burst. The read module reads blocks of data from memory in either an interleaved fashion or a non-interleaved fashion in accordance with the control information.