Abstract: A line driver selectively drives one of two transmission lines. The line driver includes a differential amplifier connected to first and second differential switches. The first differential switch is connected between an output of the differential amplifier and a first of two transmission lines. The second differential switch is connected to the output of the differential amplifier and to the second of two transmission lines. The first and second differential switches are controlled by respective first and second control signals. The output of the differential amplifier is connected to either the first or the second transmission line in response to the first and second control signals. The differential switches include loopback protection to an prevent an incoming signal from passing from one transmission line to another during power down mode.

Abstract: A power efficient and reduced electromagnetic interference (EMI) emissions transmitter for unshielded twisted pair (UTP) data communication applications. Transmit data is processed by a digital filter. The digital filter output data is converted to a current-mode analog waveform by a digital-to-analog converter (DAC). The digital filter is integrated with the DAC binary decoder in a memory device such as a ROM with time multiplexed output. DAC line driver cells are adaptively configurable to operate in either a class-A or a class-B mode depending on the desired operational modality. A discrete-time analog filter is integrated with the DAC line driver to provide additional EMI emissions suppression. An adaptive electronic transmission signal cancellation circuit separates transmit data from receive data in a bidirectional communication system operating in full duplex mode.

Abstract: A network switch for network communications includes a first data port interface supporting a plurality of data ports transmitting and receiving data at a first data rate. A second data port interface supports a plurality of data ports transmitting and receiving data at a second data rate. A CPU interface is configured to communicate with a CPU, and an internal memory communicates with the first data port interface and the second data port interface. A memory management unit is provided, including an external memory interface, for communicating data from at least one of the first data port interface and the second data port interface and an external memory. A communication channel is provided, for communicating data and messaging information between the first data port interface, the second data port interface, the internal memory, and the memory management unit.

Abstract: Methods and systems for improved feedback processing in delta-sigma modulators, including single bit and multi-bit delta-sigma modulators, continuous-time and discrete-time delta-sigma modulators, and digital and/or analog feedback loops. One or more processes are performed in a pipeline having a higher throughput rate than a throughput rate of a delta-sigma modulator. Any of a variety of processes and combinations of processes can be performed in the pipeline including, without limitation, quantization, digital signal processing, and/or feedback digital-to-analog conversion.

Abstract: A system for measuring power of a circuit on a printed circuit board (PCB) including first and second circuits, a power strip, a power plane, and a calibration strip. The power strip is connected to the power plane to the first circuit, is embedded in the PCB during the manufacturing process, and also has at least two vias for measuring a voltage drop. The calibration strip is also embedded in the PCB during the manufacturing process and has at least two vias for measuring a voltage drop. The second circuit is configured to measure a voltage drop across the power strip as a first voltage and a voltage drop across the calibration strip as a second voltage, and to calculate the power being fed to the first circuit based on the first voltage and the second voltage.

Abstract: A method for refreshing data in a circuit element included in a dynamic register. A static loop is coupled to the circuit element as a feedback path from the output terminal to the input terminal of the circuit element. A control signal is provided to the static loop. The static loop is activated via the control signal to refresh the data in the circuit element.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip includes a display engine that processes graphics images organized as windows. The display engine processes graphics images formatted in any one of a plurality of formats including a color look up table (CLUT) format. A color look-up (CLUT) table loading mechanism preferably facilitates the transfer of real-time CLUT table data during graphics composition. The loading mechanism may be triggered by a window descriptor that contains a color look-up table load command.

Abstract: A cable modem system and method are provided for using a data compression dictionary to transmit compressed payload data in a DOCSIS network while utilizing conventional cable modem termination system (CMTS) equipment. A cable modem system in accordance with the invention includes a cable modem and a CMTS adapted to send and receive compressed payload data. In one example, the cable modem is adapted to compress PDU payload data using a data compression dictionary and the CMTS is adapted to reconstruct the compressed PDU payload data that is received from the cable modem.

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.

Abstract: A system and method for providing a sort in a computer system is disclosed. The sort is based on a plurality of values of a key. Each of the plurality of items has an associated value of the plurality of values. The method and system include providing a new item of the plurality of items to a plurality of sort cells. The new item includes a new value of the plurality of values. The plurality of sort cells is for sorting the plurality of items. Each sort cell is for sorting a corresponding item of the plurality of items. The corresponding item has a corresponding value of the plurality of values. The method and system further include comparing the new value to the corresponding value for each of the plurality of sort cells to determine whether to retain the corresponding item. Each of the plurality of sort cells retains the corresponding item if the corresponding item is to be retained.

Abstract: A method for enhancing the bit rate and/or margin at which quadrature amplitude modulation (QAM) communication is performed includes the steps of varying a spectral allocation and constellation size with which communication is performed, so as to define a combination of spectral allocation and constellation size at which the bit rate and/or margin are enhanced. The spectral allocation can be varied by varying a stop frequency thereof, while maintaining a substantially constant start frequency, so as to mitigate undesirable high frequency content of the bandwidth. Alternatively, both start and stop frequencies may be varied.

Abstract: A programmable divider includes a synchronous counter configured to process an input clock signal and produce first output signals in response the input clock signal. A number of logic devices are coupled to the synchronous counter and configurable to receive the first output signals and correspondingly produce second output signals. Also included is a multiplexer that is configured to receive the second output signals and has an output coupled to an input of the synchronous counter. In the programmable divider, characteristics of the synchronous counter are selectable based upon a particular number of the logic devices configured.

Abstract: A method and a system for decoding information signals encoded by a multi-state encoding architecture and transmitted over a multi-dimensional transmission channel by computing a distance of a received word from a codeword. One-dimensional (1D) input signals are detected in a symbol decoder, implemented using look-up tables, to produce a pair of 1D errors, with each representing a distance metric between the input signal and a symbol in one of two disjoint symbol-subsets. The symbol decoder is implemented as a pair of slicers, each detecting an input signal with respect to one of two disjoint symbol-subsets. A third slicer detects the input with respect to the union of the two disjoint symbol-subsets. Decisions from the first, second and third slicers are processed to define 1D square error terms expressed in Hamming metrics. Reduced bit count error terms allow follow-on error processing to be performed with a minimum of computational complexity.

Abstract: An adaptive electronic transmission signal cancellation circuit for separating transmit data from receive data in a bidirectional communication system operating in full duplex mode is disclosed. The output of a main transmitter responsive to a first bias current is connected to the output of a receiver through an internal resistor. A first replica transmitter responsive to a second bias current and matched to the main transmitter current gain and rise/fall time characteristics is connected to the input terminal of the receiver, and produces a cancellation voltage between the output terminal of the main transmitter and the input terminal of the receiver as a function of the second bias current and the internal resistor.

Abstract: A memory management method that has the steps of assigning pointers to free memory locations and linking the pointers to one another creating a linked list of free memory locations having a beginning and an end. A free head pointer is assigned to a memory location indicating the beginning of free memory locations and a free tail pointer is assigned to a memory location indicating the end of free memory locations. An initial data pointer is assigned to the memory location assigned to the free head pointer and an end of data pointer is assigned to a last data memory location. The free head pointer is assigned to a next memory location linked to the last data memory location assigned to the end of data pointer. The next memory location indicates the beginning of free memory locations.

Abstract: A system and method for providing antialiasing of a graphical image on a display is disclosed. The graphical image is generated from data describing at least one object. The display includes a plurality of pixels. The at least one object includes a plurality of fragments. A portion of the plurality of fragments intersects a pixel of the plurality of pixels. Each of the plurality of fragments including an indication of a portion of a corresponding pixel that is intersected. The system and method include providing at least one active region for the pixel. The at least one active region intersects a first portion of the pixel. The method and system also include providing at least one new region. A first portion of the at least one new region indicates where in the pixel the at least one active region and the fragment intersect. A second portion of the at least one new region indicates where in the pixel the at least one active region and the fragment do not intersect.

Abstract: An electronic, programmable filter is disclosed which selectively removes interference, noise or distortion components from a frequency band without perturbing any of the other signals of the band. An input frequency band such as a television channel spectrum is initially demodulated to baseband and applied to the input of the filter. The baseband spectrum is combined in a complex mixer with a synthesized frequency signal that shifts the spectrum a characteristic amount, in the frequency domain, so as to position an interference component in the region about DC. Once shifted, the frequency components about DC are removed by DC canceler circuit and the resulting spectrum is mixed with a subsequent synthesized frequency signal which shifts the spectrum back to its original representation and baseband. The frequency signals are developed by a programmable frequency synthesizer which a user may program with an intelligence signal that defines the frequency location of an interference signal within the spectrum.

Abstract: The invention is table search device having a table that has a plurality of entries and a cache having a subset of entries of the plurality of entries of the table. A search engine is configured to first search the cache in a first number of search cycles and then search the table in a second number of search cycles based on search results of the cache. The search engine connected to the table and the cache.

Abstract: Digital packets, defined by a sync byte and then 130 MPEG2 compressed QPSK signal bytes, from a satellite transponder are reformatted prior to transmission to television receivers in apartments in a building wired to distribute video signals. A side byte between such sync and signal bytes in each packet indicates (a) any QPSK packet uncorrectable error and (b) processing information which allows automatic reconfiguration at the settop box. Additional FEC bytes correct to 8 errors within a MPEG2QPSK packet. The system removes the FEC bytes and reframes the MPEG2QPSK packets into a superpacket by converting a first number of the MPEG2QPSK packets to a second number of MPEG2QAM packets. An added sync byte indicates the beginning of each such MPEG2QAM packet. The system adds side data bytes including any uncorrectable errors in each MPEG2QPSK packet and adds a new, less complicated FEC to each MPEG2QAM packet.

Abstract: A system for encrypting and decrypting data formed of a number of bytes using the ARCFOUR encryption algorithm is disclosed. The system includes a system bus and an encryption accelerator arranged to execute the encryption algorithm coupled to the system bus. A system memory coupled to the system bus arranged to store a secret key array associated with the data and a central processing unit coupled to the system bus wherein encryption accelerator uses substantially no central processing unit resources to execute the encryption algorithm.