Patents Assigned to Broadcom Corporation
  • Patent number: 6295012
    Abstract: High-performance, digital-to-analog conversion (DAC) suitable for use in systems implemented with low-voltage, low-power integrated circuit fabrication processes is disclosed. Encoder circuitry receives a binary number for which an analog representation is sought. Segments of the binary number are thermometer encoded and complemented to provide signals to drive analog conversion circuitry. The analog conversion circuitry includes sets of current cells, with each cell in a set contributing an equal amount to one or the other of the complementary legs of the analog output of the converter. Each current cell is a fully differential current switch with charge canceling, fed by a regulated cascode current source. The regulated cascode current source offers uncharacteristically high impedance that contributes to good circuit performance even in low-voltage, low-power implementations. Other design factors of the current cell contribute significantly to overall performance.
    Type: Grant
    Filed: August 25, 1999
    Date of Patent: September 25, 2001
    Assignee: Broadcom Corporation
    Inventor: David Vetea Greig
  • Publication number: 20010022813
    Abstract: A system for reducing the complexity of an adaptive decision feedback equalizer, for use in connection with a dual-mode QAM/VSB receiver system is disclosed. QAM and VSB symbols, which are expressed in two's compliment notation, include an extra bit required to compensate for a fixed offset term introduced by the two's compliment numbering system. A decision feedback equalizer includes a decision feedback filter section which operates on symbolic decisions represented by a wordlength which excludes the added bit representing the offset. The vestigal word is convolved with the decision feedback filter's coefficients, while a DC component, corresponding to the excluded bit, is convolved with the same coefficient values in a correction filter. The two values are summed to provide an ISI compensation signal at the input of a decision device such as a slicer. A DC component representing a pilot tone in VSB transmission systems also introduces a DC component, and additional bits, to a VSB wordlength.
    Type: Application
    Filed: February 27, 2001
    Publication date: September 20, 2001
    Applicant: Broadcom Corporation
    Inventors: Loke Kun Tan, Tian-Min Liu, Hing Ada T. Hung
  • Patent number: 6289047
    Abstract: A method for dynamically regulating the power consumption of a high-speed integrated circuit which includes a multiplicity of processing blocks. A first metric and a second metric, which are respectively related to a first performance parameter and a second performance parameter of the integrated circuit, are defined. The first metric is set at a pre-defined value. Selected blocks of the multiplicity of processing blocks are disabled in accordance with a set of pre-determined patterns. The second metric is evaluated, while the disabling operation is being performed, to generate a range of values of the second metric. Each of the values corresponds to the pre-defined value of the first metric. A most desirable value of the second metric is determined from the range of values and is matched to a corresponding pre-determined pattern. The integrated circuit is subsequently operated with selected processing blocks disabled in accordance with the matching pre-determined pattern.
    Type: Grant
    Filed: September 3, 1999
    Date of Patent: September 11, 2001
    Assignee: Broadcom Corporation
    Inventors: Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, Henry Samueli
  • Patent number: 6288604
    Abstract: An amplifier circuit is responsive to an input data signal which is substantially DC balanced. The amplifier circuit is operative to generate an amplified data signal, and includes: a limiting amplifier responsive to the input data signal and to an error correcting signal, the limiting amplifier being operative to generate the amplified data signal; a feed back circuit responsive to a signal proportional to the amplified data signal, the feed back circuit being operative to generate the error correcting signal. The feed back circuit includes: a low pass filter responsive to the signal proportional to the amplified data signal, and operative to generate a filtered signal; and an error amplifier responsive to the filtered signal, and operative to provide the error correcting signal to the limiting amplifier; whereby offset voltage caused by process characteristics of the limiting amplifier, and temperature variations in the limiting amplifier are canceled by the error correcting feedback signal.
    Type: Grant
    Filed: February 3, 1999
    Date of Patent: September 11, 2001
    Assignee: Broadcom Corporation
    Inventors: Cheng-chung Shih, Jiann-chyi Shieh
  • Publication number: 20010019581
    Abstract: A startup protocol is provided for use in a communications system having a communications line with a master transceiver at a first end and a slave transceiver at a second end, each transceiver having a noise reduction system, a timing recovery system and at least one equalizer all converging at startup of the system. The operation of the startup protocol is partitioned into stages. The first stage includes the step of converging the equalizer and the timing recovery system of the slave while converging the noise reduction system of the master. Upon completion of the first stage the protocol enters a second stage which includes the step of converging the equalizer and the timing recovery system of the master, converging the noise reduction system of the slave, freezing the timing recovery system of the slave, and resetting the noise reduction system of the master.
    Type: Application
    Filed: February 12, 2001
    Publication date: September 6, 2001
    Applicant: Broadcom Corporation
    Inventor: Oscar E. Agazzi
  • Publication number: 20010019584
    Abstract: A method and a system for providing ISI compensation to an input signal in a bifurcated manner. ISI compensation is provided in two stages, a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel. First stage ISI compensation is performed in an inverse response filter having a characteristic feedback gain factor K, during system start-up. Second stage ISI compensation is performed by a single DFE in combination with a MDFE operating on tentative decisions output from a Viterbi decoder. As the DFE of the second stage reaches convergence, the feedback gain factor K of the first stage is ramped to zero.
    Type: Application
    Filed: May 15, 2001
    Publication date: September 6, 2001
    Applicant: Broadcom Corporation
    Inventors: Oscar E. Azazzi, David Kruse, Arthur Abnous, Mehdi Hatamian
  • Patent number: 6285865
    Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.
    Type: Grant
    Filed: November 12, 1999
    Date of Patent: September 4, 2001
    Assignee: Broadcom Corporation
    Inventors: Pieter Vorenkamp, Klaas Bult, Frank Carr
  • Patent number: 6285348
    Abstract: A method and system for providing antialiasing of a graphical image on a display from data describing at least one object is disclosed. The display includes a plurality of pixels. The method and system include providing a plurality of fragments for the at least one object. A portion of the plurality of fragments intersects a pixel of the plurality of pixels. Each of the plurality of fragments includes a depth value, a slope of the depth value, and an indication of a portion of a corresponding pixel that is intersected. The method and system include calculating a plurality of subpixel depth values for a fragment of the plurality of fragments. The plurality of subpixel depth values is calculated using the depth value and the slope of the depth value of the fragment. The method and system include determining whether to store a portion of the fragment based on the plurality of subpixel depth values for the fragment and the indication of the extent the corresponding pixel is intersected by the fragment.
    Type: Grant
    Filed: April 22, 1999
    Date of Patent: September 4, 2001
    Assignee: Broadcom Corporation
    Inventor: Michael C. Lewis
  • Patent number: 6272173
    Abstract: A method for reducing a propagation delay of a digital filter. The digital filter has an input path and an output path and includes a set of delay elements and a number of taps. The taps couples the input path to the output path. Each of the taps includes a coefficient, a multiplier and an adder. Each of the delay elements is disposed between two adjacent taps. The delay elements are placed in both the input path and the output path of the digital filter, such that the digital filter has fewer delay elements in the input path than a direct-form digital filter having the same number of taps in a direct-form structure and has fewer delay elements in the output path than a transposed-form digital filter having the same number of taps in a transposed-form structure, and such that the digital filter has same transfer function as the direct-form digital filter and the transposed-form digital filter.
    Type: Grant
    Filed: November 9, 1999
    Date of Patent: August 7, 2001
    Assignee: Broadcom Corporation
    Inventor: Mehdi Hatamian
  • Patent number: 6268816
    Abstract: Binary indications are converted to an analog representation with significant reduction in ringing at the transitions between successive binary indications and in the period during each binary indication. The binary indications are disposed in a row-and-column matrix to provide a thermometer code. Each stage of the converter includes a decoder and latch arranged so the decoder inputs settle before the latch is set by the clock pulses. The stages are implemented in complementary CMOS. Complementary transistors are biased so one transistor of the pair is driven to the rail while the other transistor of the pair floats. A dummy CMOS transistor is used to balance the number of transistors in the decoder paths.
    Type: Grant
    Filed: January 3, 2001
    Date of Patent: July 31, 2001
    Assignee: Broadcom Corporation
    Inventors: Klaas Bult, Chi-Hung Lin
  • Publication number: 20010010096
    Abstract: Requests are processed to transmit data packets upstream from a cable modem to a cable headend in a manner that minimizes the use of CPU operations and/or memory capacity. Data packets to be transmitted upstream are stored at the cable modem. The data packets each have a given transmission data byte length value. Burst profiles are received successively at the cable modem. Each time a new bust profile is received, a set of physical data length values corresponding to respective transmission data byte length values is calculated from the parameters of the received burst profile. The calculated set of physical data length values is stored in memory so the individual values can be retrieved from the transmission data byte length values again and again, rather than being re-calculated each time a conversion is made from transmission data byte length values to physical data length values. The same set of physical data length values is used until a new burst profile is received by the cable modem.
    Type: Application
    Filed: February 27, 2001
    Publication date: July 26, 2001
    Applicant: Broadcom Corporation
    Inventors: John Daniel Horton, Scott Hollums, Chris Roussel
  • Publication number: 20010008430
    Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.
    Type: Application
    Filed: January 19, 2001
    Publication date: July 19, 2001
    Applicant: Broadcom Corporation
    Inventors: Frank Carr, Pieter Vorenkamp
  • Patent number: 6259745
    Abstract: A power efficient and reduced electromagnetic interference (EMI) emissions transmitter for unshielded twisted pair (UTP) data communication applications. Transmit data is processed by a digital filter. The digital filter output data is converted to a current-mode analog waveform by a digital-to-analog converter (DAC). The digital filter is integrated with the DAC binary decoder in a memory device such as a ROM with time multiplexed output. DAC line driver cells are adaptively configurable to operate in either a class-A or a class-B mode depending on the desired operational modality. A discrete-time analog filter is integrated with the DAC line driver to provide additional EMI emissions suppression. An adaptive electronic transmission signal cancellation circuit separates transmit data from receive data in a bidirectional communication system operating in full duplex mode.
    Type: Grant
    Filed: October 29, 1999
    Date of Patent: July 10, 2001
    Assignee: Broadcom Corporation
    Inventor: Kevin T. Chan
  • Patent number: 6253345
    Abstract: A method and a system for decoding information signals encoded in accordance with a multi-state encoding scheme and transmitted over a multi-dimensional transmission channel by computing a distance of a received word from a codeword. One-dimensional (1D) input signals are processed in a pair of symbol decoders, implemented as look-up tables, to produce a pair of 1D errors, with each representing a distance metric between the input signal and a symbol in one of two disjoint symbol-subsets. The 1D errors are combined based on the multi-state encoding scheme in order to produce a set of multi-dimensional error terms. Each of the multi-dimensional error terms corresponds to a distance between a received word and a nearest codeword.
    Type: Grant
    Filed: August 9, 1999
    Date of Patent: June 26, 2001
    Assignee: Broadcom Corporation
    Inventors: Oscar E. Agazzi, David Kruse, Arthur Abnous, Mehdi Hatamian
  • Patent number: 6252904
    Abstract: A method and a system for providing an input signal from a multiple decision feedback equalizer to a decoder based on a tail value and a subset of coefficient values received from a decision-feedback equalizer. A set of pre-computed values based on the subset of coefficient values is generated. Each of the pre-computed values is combined with the tail value to generate a tentative sample. One of the tentative samples is selected as the input signal to the decoder. In one aspect of the system, tentative samples are saturated and then stored in a set of registers before being outputted to a multiplexer which selects one of the tentative samples as the input signal to the decoder.
    Type: Grant
    Filed: August 9, 1999
    Date of Patent: June 26, 2001
    Assignee: Broadcom Corporation
    Inventors: Oscar E. Agazzi, David Kruse, Arthur Abnous, Mehdi Hatamian
  • Patent number: 6249544
    Abstract: A method and a system for providing ISI compensation to an input signal in a bifurcated manner. ISI compensation is provided in two stages, a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel. First stage ISI compensation is performed in an inverse response filter having a characteristic feedback gain factor K, during system start-up. Second stage ISI compensation is performed by a single DFE in combination with a MDFE operating on tentative decisions output from a Viterbi decoder. As the DFE of the second stage reaches convergence, the feedback gain factor K of the first stage is ramped to zero.
    Type: Grant
    Filed: August 9, 1999
    Date of Patent: June 19, 2001
    Assignee: Broadcom Corporation
    Inventors: Oscar E. Azazzi, David Kruse, Arthur Abnous, Mehdi Hatamian
  • Patent number: 6246692
    Abstract: A packet switching fabric includes a data ring, a control ring, a plurality of network links each coupled to at least one network node, and a plurality of switching devices coupled together by the data ring and the control ring so that the network links can be selectively communicatively coupled.
    Type: Grant
    Filed: June 5, 1998
    Date of Patent: June 12, 2001
    Assignee: Broadcom Corporation
    Inventors: William Dai, Jason Chao, Cheng-chung Shih
  • Patent number: 6246256
    Abstract: A queue length arbiter system provides for selecting from a plurality of N queues requiring access to a resource. The system includes: an arbitration circuit; and a plurality of weight circuits each being associated with a corresponding one of the queues, and being operative to store a corresponding weight count value, and also being operative to initialize the corresponding weight count value to a corresponding initial weight value determined based on a length value indicative of a number of data portions enqueued at the corresponding queue at an initial time, and being further operative to decrease the corresponding weight count value in response to a corresponding one of a plurality of grant signals, and also being operative to generate a corresponding one of a plurality of weight count signals, the corresponding weight count signal carrying the corresponding weight count value.
    Type: Grant
    Filed: November 29, 1999
    Date of Patent: June 12, 2001
    Assignee: Broadcom Corporation
    Inventors: Yao-Ching Liu, William Dai, Jason Chao, Jun Cao
  • Publication number: 20010002923
    Abstract: A method and a system for decoding information signals encoded by a multi-state encoding architecture and transmitted over a multi-dimensional transmission channel by computing a distance of a received word from a codeword. One-dimensional (1D) input signals are detected in a symbol decoder, implemented using look-up tables, to produce a pair of 1D errors, with each representing a distance metric between the input signal and a symbol in one of two disjoint symbol-subsets. The symbol decoder is implemented as a pair of slicers, each detecting an input signal with respect to one of two disjoint symbol-subsets. A third slicer detects the input with respect to the union of the two disjoint symbol-subsets. Decisions from the first, second and third slicers are processed to define 1D square error terms expressed in Hamming metrics. Reduced bit count error terms allow follow-on error processing to be performed with a minimum of computational complexity.
    Type: Application
    Filed: January 22, 2001
    Publication date: June 7, 2001
    Applicant: Broadcom Corporation
    Inventors: Oscar E. Agazzi, David Kruse, Arthur Abonous, Mehdi Hatamian
  • Patent number: 6236645
    Abstract: A communication line having a plurality of twisted wire pairs connects a plurality of transmitters, one transmitter at each end of each twisted wire pair, with a plurality of receivers, one receiver at each end of each twisted wire pair. Each receiver receives a combination signal including a direct signal from the transmitter at the opposite end of the twisted wire pair with which the receiver is associated and a plurality of far-end crosstalk (FEXT) impairment signals, one from each of the remaining transmitters at the opposite end of the communications line. A plurality of FEXT cancellation systems, one associated with each receiver, provides a replica FEXT impairment signal. A device associated with each receiver is responsive to the combination signal received by the receiver and the replica FEXT impairment signal provided by the FEXT cancellation system associated with the receiver for substantially removing the FEXT impairment signals from the combination signal.
    Type: Grant
    Filed: March 9, 1998
    Date of Patent: May 22, 2001
    Assignee: Broadcom Corporation
    Inventor: Oscar E. Agazzi