Abstract: A bistable device has first and second complementary input terminals and first and second bistable states that are determined by the polarity of the signal applied to one of the input terminals. A source of an uninverted binary input signal, preferably an uninverted data stream, has a first value or a second value. A source of an inverted binary input signal, preferably an inverted data stream, has a first value or a second value in complementary relationship to the values of the uninverted input signal. A first source of a trigger signal has one polarity. A second source of a trigger signal has the other polarity. The first trigger signal is applied to the first input terminal and the second trigger signal is applied to the second input terminal to drive the bistable device into the first stable state when the input signal has the first value.

Abstract: A communications network switch includes a plurality of network ports for transmitting and receiving packets to and from network nodes via network links, each of the packets having a destination address and a source address, the switch being operative to communicate with at least one trunking network device via at least one trunk formed by a plurality of aggregated network links. The communications network switch provides a method and apparatus for balancing the loading of aggregated network links of the trunk, thereby increasing the data transmission rate through the trunk.

Abstract: A method and a timing recovery system for generating a set of clock signals in a system which includes a set of subsystems. Each of the subsystems includes an analog section. The set of clock signals includes a set of sampling clock signals. Each of the analog sections operates in accordance with a corresponding one of the sampling clock signals. For each of the sampling clock signals, a phase error is generated from a corresponding phase detector. The phase errors are filtered by a set of corresponding loop filters. The filtered phase errors are provided to a set of corresponding oscillators to generate phase control signals. The phase control signals are provided to a set of corresponding phase selectors to generate the sampling clock signals.

Abstract: A switch assembly having multiple blades in a chassis and a method of using that assembly to switch data is disclosed. A network switch assembly for network communications includes at least one fabric blade and a plurality of port blades. The at least one fabric blade has at least one switch having a plurality of data port interfaces, supporting a plurality of fabric data ports transmitting and receiving data, and a CPU interface, where CPU interface is configured to communicate with a CPU. The at least one fabric blade also has a CPU subsystem communicating with the CPU interface. Each of said plurality of port blades has at least one switch having a plurality of data port interfaces, supporting a plurality of port data ports transmitting and receiving data.

Abstract: A switch is configured to block packets from being transmitted through designated ports. The switch has port bitmap generator configured to obtain a port bitmap and a table is configured to store a block mask indicating which port the packet should not be transmitted. A block mask lookup is configured to determine the block mask for the packet from the table, and a transmit port bitmap generator is configured to determine which ports the packet should be transmitted using the port bitmap and the block mask.

Abstract: The present invention relates to electrostatic discharge (ESD) protection and, more particularly, to methods and systems for improving response times of ESD triggering and clamping circuitry. An ESD protection circuit protects ESD circuitry from direct current (DC) voltage stress during normal operations by reducing terminal pad voltage level. A frequency bypass circuit implemented across an ESD protection circuit essentially acts as a short circuit during ESD events and essentially acts as an open circuit during normal operations. A frequency bypass circuit implemented in conjunction with an ESD protection circuit enables ESD triggering and clamping circuitry to react to ESD events without undue delay. Unlike an ESD protection circuit, a frequency bypass circuit does not result in substantial voltage reduction across its terminals. In an embodiment, the frequency bypass circuit includes one or more capacitors.

Abstract: A data switch for network communications includes at least one first data port interface which supports a plurality of data ports which transmit and receive data at a first data rate. At least one second data port interface is provided; the at least one second data port interface supports a plurality of data ports transmitting and receiving data at a second data rate. A CPU interface is provided, with the CPU interface configured to communicate with a CPU. An internal memory is provided, and communicates with the at least one first data port interface and the at least one second data port interface. A memory management unit is provided, and includes an external memory interface for communicating data from at least one of the first data port interface and the second data port interface and an external memory.

Abstract: A source-follower transistor based buffer provides high linearity. A replica transistor is used to generate a replica voltage substantially equal to the output voltage of the buffer. The replica voltage is level shifted by a level shift circuit and applied at the drain of the source-follower transistor to improve the linearity of the buffer. The buffer may be used in conjunction with a switched-capacitor sampling circuit. A damping circuit may be used to reduce charge glitches due to sampling. The damping circuit may be a low pass filter. The buffer may be used in an interface circuit that produces an output signal from an input signal and controls the level of the output signal.

Abstract: A method and system for processing textures for a graphical image on a display is disclosed. The graphical image includes a plurality of polygons. Each of the plurality of polygons includes at least one fragment. The fragment includes at least one texture and a w-value for the fragment. Each polygon has a plurality of vertices, a display area, and a texture space area. Each of the vertices has a vertex w-value. The at least one texture is associated with at least one MIP map. The MIP map includes a plurality of MIP map levels. The method and system include determining a selection value for each fragment of a polygon of the plurality of polygons. The selection value includes ½ multiplied by the base two logarithm of the texture area divided by the display area and divided by the product of the vertex w-values for each of the plurality of vertices. The selection value also includes 3/2 multiplied by the base two logarithm of the w-value for each of the at least one fragment.

Abstract: A network switch that has a plurality of input ports that receive data packets. An external interface is connected to the plurality of input ports. The external interface externally transmits the data packets for processing, and receives the data packets after processing. A memory management unit is connected to the external interface and a plurality of output ports are connected to the memory management unit.

Abstract: A method for dynamically regulating the power consumption of a high-speed integrated circuit which includes a multiplicity of processing blocks. A first metric and a second metric, which are respectively related to a first performance parameter and a second performance parameter of the integrated circuit, are defined. The first metric is set at a pre-defined value. Selected blocks of the multiplicity of processing blocks are disabled in accordance with a set of pre-determined patterns. The second metric is evaluated, while the disabling operation is being performed, to generate a range of values of the second metric. Each of the values corresponds to the pre-defined value of the first metric. A most desirable value of the second metric is determined from the range of values and is matched to a corresponding pre-determined pattern. The integrated circuit is subsequently operated with selected processing blocks disabled in accordance with the matching pre-determined pattern.

Abstract: Provided is a switched capacitor feedback circuit including two or more input ports configured to receive a corresponding a number of input signals and at least one output port. The output port is configured to output an adjusting signal. The input signals includes a number of primary signals and two or more reference signals that are associated with a first timing phase of operation. The adjusting signal is produced based upon a comparison between the primary signals the reference signals. Also provided is a pair of active devices having gates coupled together and structured to receive the adjusting signal. The active devices are configured to provide a gain to the adjusting signal in accordance with a predetermined gain factor, and facilitate an adjustment to the number of primary signals based upon the gain during a second timing phase of operation.

Abstract: A method and circuit for adjusting clock pulse widths in a high speed sample and hold circuit. A single phase clock signal is input into a pulse discriminator and separated into rising and falling edges. The edges are adjusted to a desired slope. The adjusted edges and the unadjusted edges are summed and output as multiple clock signals with a desired pulse edge alignment. The clock signals control switches in a manner to reduce signal dependent sampling distortion.

Abstract: A circuit and method for bridging an analog signal between two integrated circuits operating at different supply voltages. The circuit is a two stage fixed gain amplifier. The first stage is a transconductance amplifier and the second stage is an operational amplifier. The first stage converts an input signal from a voltage into a current. The second stage converts the current signal to an output voltage signal.

Abstract: A telephony system and method is provided that reduces delay and provides better utilization of upstream bandwidth in delivering packet telephony services to a plurality of subscriber lines via a cable modem system. An exemplary system includes a plurality of voice processing modules, a host processor, and a buffer. Each voice processing module receives digital voice signals from a separate set of subscriber lines, compresses the digital voice signals to generate a voice packet, and transfers the voice packet to the buffer. The host processor then assembles a packet by concatenating the voice packets and transmits the assembled packet for delivery over a data network. Because the plurality of voice processing modules process the voice packets in parallel, delay is reduced in the assembly and transmission of the assembled packet.

Abstract: Provided is a circuit to convert input CMOS level signals having a predetermined duty cycle to CML level signals having a higher duty cycle. The circuit includes two differential transistor pairs connected together. The two differential pairs are constructed and arranged to use gates of the associated transistors as inputs to receive and combine a number of phase shifted CMOS input signals. The combined CMOS input signal are converted to CML level signals which are provided as circuit outputs.

Abstract: A low voltage current mirror circuit (also referred to as a bias circuit) for establishing a plurality of bias voltages from an input current supplied to an input terminal of the circuit includes an input stage, a current stage connected to the input stage, a feedback stage connected to the current stage, a reference bias stage connected to the feedback stage and the current stage. The circuit establishes first and second bias voltages suitable for biasing current sources of a first type, and third and fourth bias voltages suitable for biasing current sources of a second type complementary to the first type. The bias voltages track the input current over variations in at least one of process, temperature and power supply voltage.

Abstract: An electronic, programmable filter is disclosed which selectively removes interference, noise or distortion components from a frequency band without perturbing any of the other signals of the band. An input frequency band such as a television channel spectrum is initially demodulated to baseband and applied to the input of the filter. The baseband spectrum is combined in a complex mixer with a synthesized frequency signal that shifts the spectrum a characteristic amount, in the frequency domain, so as to position an interference component in the region about DC. Once shifted, the frequency components about DC are removed by DC canceler circuit and the resulting spectrum is mixed with a subsequent synthesized frequency signal which shifts the spectrum back to its original representation and baseband. The frequency signals are developed by a programmable frequency synthesizer which a user may program with an intelligence signal that defines the frequency location of an interference signal within the spectrum.

Abstract: Digital signal processing based methods and systems for receiving electrical and/or optical data signals include electrical receivers, optical receivers, parallel receivers, multi-channel receivers, timing recovery schemes, and, without limitation, equalization schemes. The present invention is implemented as a single path receiver. Alternatively, the present invention is implemented as a multi-path parallel receiver in which an analog-to-digital converter (“ADC”) and/or a digital signal processor (“DSP”) are implemented with parallel paths that operate at lower rates than the received data signal. In an embodiment, a parallel DSP-based receiver in accordance with the invention includes a separate timing recovery loop for each ADC path. The separate timing recovery loops can be used to compensate for timing phase errors in the clock generation circuit that are different for each path.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic with inductive broadbanding fabricated in conventional CMOS process technology. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with inductive broadbanding/C3MOS logic with low power conventional CMOS logic. The combined C3MOS logic with inductive broadbanding/C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.