Abstract: Low Density Parity Check (LDPC) code decoder using min*, min**, max* or max** and their respective inverses. For the first time, min* processing is demonstrated for use in decoding LDPC-coded signals. In addition, max*, min**, or max** (and their respective inverses) may also be employed when performing calculations that are required to perform decoding of signals coded using LDPC code. These new parameters may be employed to provide for much improved decoding processing for LDPC codes when that decoding involves the determination of a minimal and/or maximal value, or a minimal and/or maximal log corrected value, from among a number of possible values. The total number of processing steps employed within the decoding of an LDPC-coded signal is significantly reduced be employing the min*, max*, min**, or max** (and their respective inverses) decoding processing described herein.

Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

Abstract: A method and apparatus for optimizing access to memory, wherein the method includes the steps of receiving a first request for access to a memory, receiving at least two additional requests for access to the memory, and determining a first clock overhead associated with the first request for access to the memory. The method further includes the steps of determining an additional clock overhead associated with each of the at least two additional requests for access to the memory in conjunction with the first request, determining a combination of requests that can be processed together using an optimized overhead, and processing the combination of requests as a single request with the optimal overhead.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic with inductive broadbanding fabricated in conventional CMOS process technology. Optimum balance between power consumption and speed for each circuit application is achieved by combining high speed C3MOS logic with inductive broadbanding/C3MOS logic with low power conventional CMOS logic. The combined C3MOS logic with inductive broadbanding/C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: A motion detector (300) detects motion of images represented by video pixels. A first motion detector (320) is arranged to generate first motion signals (S) representing detected motion of images represented by the pixel values. A second motion detector (360) is arranged to modify the first motion signals to generate corrected motion signals (S?) in response to the relationship of a pixel being processed to a change of motion of one or more of the image in the vertical direction. The second motion detector also modifies the first motion signals in response to the value of the pixel being processed.

Abstract: A method for setting indicators in a control store of a computer system for conditionally performing operations, comprises providing a control store setting instruction defining an execution condition and specifying a control store to be set according to the condition, specifying in the instruction an operand lane size over which a setting operation is to be performed, the operand lane size specified being selected from a plurality of predetermined operand lane sizes, performing the setting operation defined in the setting instruction on a per operand lane basis over a plurality of operand lanes, writing the result of the setting operation to the control store specified in the instruction to set a plurality of indicators on a lane by lane basis, wherein one or a predetermined plurality of indicators is set for each operand lane in dependence on the size of the operand lane defined in the instruction. An instruction for performing the preferred method is also disclosed.

Abstract: A method and device for testing multi-channel transceivers in an integrated circuit is provided. More specifically, the present invention relates to a method and device for implementing a built-in self-test for multi-channel transceivers. An exemplary embodiment of the present invention includes a test pattern generator, a multiplexer, a demultiplexer, and a test result evaluator. The test pattern generator generates a test pattern which is fed into each of the input channels of the multiplexer. The multiplexer multiplexes the data from all its input channels and then relays the data to the demultiplexer. The test result evaluator then individually checks the data at each of the output channels of the demultiplexer to determine whether the data received at each output channel is the same as the test pattern. In order to facilitate the checking process, signature analysis is utilized.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip includes a display engine that processes graphics images organized as windows. The display engine processes graphics images formatted in any one of a plurality of formats including a color look up table (CLUT) format. A color look-up (CLUT) table loading mechanism preferably facilitates the transfer of real-time CLUT table data during graphics composition. The loading mechanism may be triggered by a window descriptor that contains a color look-up table load command.

Abstract: Methods and systems for communicating on a wireless channel are provided which enable subscribers that share the channel to transmit using different modulation schemes. The modulation scheme used by each subscriber is assigned to the subscriber by a wireless access termination system. The modulation scheme assigned to a subscriber by the wireless access termination system is determined based on measurements of the quality of signals received from that subscriber. In one embodiment, the invention includes a transmitter and a receiver. The receiver is capable of transmitting data using one of a number of encoding and symbol constellation configurations. The receiver is also capable of receiving a first signal. Receiving the first signal causes the transmitter to transmit a second signal using a specified encoding and symbol constellation configuration.

Abstract: In accordance with the present invention, an integrated circuit system and method are provided for increasing the number of processors on a single integrated circuit to a number that is larger than would typically be possible to coordinate on a single bus. In the present invention a two-level memory coherency scheme is implemented for use by multiple processors operably connected to multiple buses in the same integrated circuit. A control device, such as node controller, is used to control traffic between the two coherency levels. In one embodiment of the invention the first level of coherency is implemented using a “snoopy” protocol and the second level of coherency is a directory-based coherency scheme. In some embodiments of the invention, the directory-based coherency scheme is implemented using a centralized memory and directory architecture. In other embodiments of the invention, the second level of coherency is implemented using distributed memory and a distributed directory.

Abstract: A transconductance device has substantially linear characteristics. The transconductance device includes a differential pair that receives a differential input voltage signal and produces a differential output current signal and a current source coupled to the differential pair. The current source produces a current having a constant portion and a variable portion, such that the derivative of the transconductance with respect to the differential input voltage is constant across a very large range of the differential input voltage and across a very high range of frequencies of the differential input signal. This linearization technique produces no extraneous noise at the differential output current.

Abstract: An input buffer for use in a differential operational amplifier is disclosed that regulates current through a main input differential pair while preventing output distortion and allowing high linearity. The input buffer includes a main input transistor pair that receives a voltage input, a tail current source, and a squeezable tail current source circuit including a single-ended self-biased folded feedback loop. These are configured such that current through the main input transistor pair is maintained as the voltage input varies. The folded feedback loop includes a folding transistor and a biasing current source that biases the folding transistor. The squeezable tail current source circuit also includes a replica transistor pair, a bias transistor, and a tail transistor pair. The biasing current source and folding transistor isolate the bias transistor and tail transistor pair from a drain voltage of the replica transistor pair, preventing output distortion and allowing high linearity.

Abstract: A first serial transceiver has a reference clock, a first transmitter, and a first receiver. The first receiver includes (i) a phase detector, and (ii) a phase rotator. The phase rotator is driven by the reference clock. A first multiplexer is coupled to the first receiver. The first multiplexer receives the phase detector output and a control signal. When the first serial transceiver is in a test configuration, the first multiplexer passes the control signal to the phase rotator, thereby varying the frequency of the phase rotator output. A second multiplexer is coupled to the first transmitter. The second multiplexer receives a reference clock signal and the phase rotator output. When the first serial transceiver is in a test configuration, the second multiplexer passes the phase rotator output to the first transmitter. The first transmitter thereby transmits a serial data stream that varies in frequency from said reference clock.

Abstract: A circuit and method for bridging an analog signal between two integrated circuits operating at different supply voltages. The circuit is a two stage fixed gain amplifier. The first stage is a transconductance amplifier and the second stage is an operational amplifier. The first stage converts an input signal from a voltage into a current. The second stage converts the current signal to an output voltage signal.

Abstract: A communication network having at least one access point supports wireless communication among a plurality of wireless roaming devices via a first and a second wireless channel. The access point comprises a first and a second transceiver. The first and second transceivers operate on the first and second wireless channels, respectively. Each of the plurality of wireless roaming devices are capable of communicating on the first and second wireless channel. In one embodiment, the first wireless channel is used to exchange data, while the second channel is used to manage such exchanges as well as access to the first channel. In an alternate embodiment, both channels are used to support communication flow, however the first channel supports a protocol that is more deterministic than that of the second channel. Allocation of ones of the plurality of wireless roaming devices from one channel to the next may occur per direction from the access point.

Abstract: Provided is an apparatus that includes an integrated circuit (IC) mounted on a chip carrier. The IC has one or more differential pair circuits coupled thereto and the chip carrier has a signal escaping portion and a remaining portion. The apparatus also includes differential signal lines coupled to the differential pair circuits, the differential signal lines (i) extending through the chip carrier and (ii) having first and second segments. The first segment extends through the escaping portion and the second segment extends through the remaining portion. The first and second segments have respective first and second widths.

Abstract: The system and method generates two clock signals, one with a 2 ns delay with respect to the other, from a single PLL to enable a RGMII.

Abstract: A hierarchical parallel pipelined circuit includes a first stage with a plurality of sampling circuits and a plurality of corresponding analog or digital circuits that receive an output from the plurality of sampling circuits. A second stage includes a second plurality of sampling circuits and a plurality of corresponding analog or digital circuits that receive an output from the plurality of sampling circuits. A multi-frequency, multi-phase clock clocks the first and second stages, the multi-frequency, multi-phase clock providing a first clock having a first frequency having either a single or plurality of phases, and a second clock having a second frequency having a plurality of phases. A first phase of a plurality of phases is phase locked to the first phase of the first clock. The clock frequency multiplied by the number of parallel devices in each stage is the throughput of the circuit and is kept constant across the stages.

Abstract: An apparatus and method for implementing an equalizer which combines the benefits of a decision feedback equalizer (DFE) with a maximum-a-posterori (MAP) equalizer (or a maximum likelihood sequence estimator, MLSE) to provide an equalization device with significantly lower complexity than a full-state MAP device, but which still provides improved performance over a conventional DFE. The equalizer architecture includes two DFE-like structures, followed by a MAP equalizer. The first DFE forms tentative symbol decisions. The second DFE is used thereafter to truncate the channel response to a desired memory of L1 symbols, which is less than the total delay spread of L symbols of the channel. The MAP equalizer operates over a channel with memory of L1 symbols (where L1<=L), and therefore the overall complexity of the equalizer is significantly reduced.

Abstract: A method and apparatus for dynamically controlling a programmable gain amplifier (PGA) in a radio receiver to provide a plurality of gain steps thereby providing automatic gain control (AGC) in a receiver intermediate frequency (IF) stage comprises an analogy peak detector formed to including a constant current source and a plurality of MOSFETs all configured to produce an output voltage (DC) whose value reflects a peak amplitude of a received differential quadrature phase shift keyed (QPSK) signal. A first circuit portion generates currents that are proportional to the square of the magnitude of the gate to source voltage for each of a plurality of MOSFETs coupled to receive the differential QPSK signal and a second circuit portion produces a voltage that is equal to the square root of the sum of the squares of the currents produced (drawn) by the MOSFETs of the first circuit portion.