Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

Abstract: A radio receiver portion of a transceiver includes a differential amplifier that is used to provide a fast response. A pair of input MOSFETs of the differential amplifier stage are coupled to an active load. A voltage follower circuit is coupled to each output stage of the two stage differential amplifier to drive a current through a load without reducing the output voltage. The voltage follower stages each include a current mirror that replicates current level defined by an input MOSFET of the voltage follower circuit and, by its configuration, a voltage level produced by the differential amplifier to the input MOSFET of the voltage follower circuit. Accordingly, the differential amplifier stage defines the amplification of the circuit while the voltage follower circuits replicate the amplified output with the ability to drive a load.

Abstract: A system on chip such as a radio receiver has reduced suceptibility to voltages in the bulk silicon by using gyrator elements in the receiver with each gyrator element including a plurality of current sources interconnected to provide output transconductance voltages, and a variable load for the current sources including first and second load resistors each serially connected with one other plurality of current sources. A variable resistance interconnects nodes of the load resistors with the variable resistance comprising a pair of native MOS transistors having low threshold voltages. In a preferred embodiment the first and second load resistors comprise first and second MOS transistors with the pair of native transistors serially connected between source elements of the first and second MOS transistors.

Abstract: A circuit for applying power to mixed mode integrated circuits in a predefined sequence. The circuit includes a first circuit powered by a first voltage and a second circuit powered by a second voltage that is less than the first voltage and having the second voltage coupled to the first circuit. The circuit for applying power to mixed mode integrated circuits includes a modified I/O cell of the second circuit. The modified I/O cell has a driver transistor including a back gate terminal, a gate terminal that is driven by the second circuit, a drain terminal that is coupled to a first circuit signal, and a source terminal that is coupled to the second voltage. The circuit for applying power to mixed mode integrated circuits further includes a controller circuit coupled to the first voltage and the second voltage supplied as controller circuit inputs. The controller circuit has a plurality of controller circuit outputs.

Abstract: Method and apparatus for performing calculations for forward (alpha) and reverse (beta) metrics in a map decoder. The method includes using a min star (min*) operation to receive the metrics and a priori values as well as forming min star structures from individual min star operations. Two separate outputs from the min star operation may be maintained separately throughout all calculations and combined only when a final value is required. In addition input to the min star operators that are available prior to a particular decoder iteration may be combined separately to allow an increase in speed within decoding iterations. The same principals apply to the more popular max star operation.

Abstract: An imaging device includes a plurality of photo-diodes arranged in a plurality of columns on a single Complementary Metal Oxide Semiconductor (CMOS) substrate. A plurality of analog-to-digital converters (ADCs) corresponding to the plurality of columns of photo-diodes are arranged on the substrate, with each ADC having an input coupled to outputs of the photo-diodes in the corresponding column. Parallel processing of the data streams produced by the multiple ADCs improves the bandwidth of the imaging device. The ADCs have one or more capacitors based on a reference capacitor that are configured so that the corresponding capacitors for different ADCs are substantially equal across the CMOS substrate. As such, image variation and streaking across the columns of photo-diodes is minimized or eliminated. The reference capacitors of the ADCs are above a minimum capacitance value, determined by a maximum variation of the reference capacitors across the substrate.

Abstract: A method of programming a memory includes the steps of attempting to program a bit at a designated address for a predetermined time; testing the bit to see if it has been programmed; increasing the predetermined time by approximately an order of magnitude; repeating the previous steps (until the bit at the designated address is programmed; and repeating all the previous steps by advancing the designated address until all bits in the memory are programmed.

Abstract: A network switch for network communications is disclosed. The switch includes a first data port interface, supporting at least one data port transmitting and receiving data at a first data rate and a second data port interface supporting a at least one data port transmitting and receiving data at a second data rate. The switch also has a CPU interface configured to communicate with a CPU and a memory management unit for communicating data from at least one of the first and second data port interfaces and a memory. It also has a communication channel for communicating data and messaging information between the first and second data port interfaces and the memory management unit and a plurality of semiconductor-implemented lookup tables including an address resolution lookup table, a layer three IP lookup table and VLAN tables.

Abstract: A method, system, and apparatus for optimizing routing layers and board space requirements for a ball grid array package is described. The ball grid array package includes a substrate material having a first side configured to receive a semiconductor chip and a second side having a plurality of conductive pads arranged in an array of rows and columns. The array of pads has at least one edge not fully populated with pads.

Abstract: A method and apparatus are disclosed for performing adaptive run-time power management in a system employing a CPU and an operating system. A CPU cycle tracker (CCT) module monitors critical CPU signals and generates CPU performance data based on the critical CPU signals. An adaptive CPU throttler (THR) module uses the CPU performance data, along with a CPU percent idle value fed back from the operating system, to generate a CPU throttle control signal during predefined run-time segments of the CPU run time. The CPU throttle control signal links back to the CPU and adaptively adjusts CPU throttling and, therefore, power usage of the CPU during each of the run-time segments.

Abstract: A one-time programming memory element, capable of being manufactured in a 0.13 ?m or below CMOS technology, having a capacitor, or transistor configured as a capacitor, with an oxide layer capable of passing direct gate tunneling current. Also included is a write switch, having first and second switches coupled to the capacitor, and a read switch also coupled to the capacitor. The capacitor/transistor is one-time programmable as an anti-fuse by application of a program voltage across the oxide layer via the write switch to cause direct gate tunneling current to rupture the oxide layer to form a conductive path having resistance of approximately hundreds of ohms or less.

Abstract: The radio frequency integrated circuit (RFIC) electrostatic discharge (ESD) circuit includes a transformer balun, an impedance matching circuit and a clamping circuit. The balun is operably coupled to transpose a single-ended radio frequency (RF) signal and differential RF signal. The balun includes a 1st winding that is coupled to the single-ended radio frequency signals and a 2nd winding that is coupled for differential RF signals. The impedance matching circuit is coupled to the 1st winding and provides, in conjunction with the impedance of the balun, impedance matching with an antenna coupled to the RFIC. The clamping circuit is operably coupled to the balun and/or to the impedance matching circuit and, in combination with the impedance matching circuit and/or in combination with the balun, provides ESD protection for the receiver section and/or transmitter section of the radio frequency integrated circuit.

Abstract: A switch, switched architecture and process for transferring data through an FCAL switch is disclosed. The switch uses multiple switch control circuits each coupled to one FCAL network and all connected to a crossbar switch. The switch control circuits are coupled together by a protocol bus for coordination purposes. Local conversations can occur on each FCAL loop and crossing conversations through the switch can occur concurrently. The OPN primitive is used to establish the connection before any data is transferred thereby eliminating the need for buffer memory in the switch control circuits. The destination address of each OPN is used to address a lookup table in each switch control circuit to determine if the destination node is local. If not, the destination is looked up and a connection request made on the protocol bus. If the remote port is not busy, it sends a reply which causes both ports to establish a data path through the backplane crossbar switch.

Abstract: A method of compensating for carrier frequency and phase errors of a received multi-carrier modulated signal. The received multi-carrier signal including modulated carriers for transmitting known data and unmodulated carriers for error correction, comprising, time domain down converting the received multi-carrier signal to base-band to provide a down-converted signal, the down-converted signal including a plurality of modulated carriers for transmitting known data and unmodulated carriers for error correction. Sampling an unmodulated carrier of the down-converted signal to provide received data samples. Providing a reference signal derived from the unmodulated carrier of the down-converted signal. And, estimating phase errors from a phase difference between the ummodulated carrier and the reference signal derived from the unmodulated carrier of the down-converted signal to provide a plurality of received sample phase error estimates for each modulated carrier.

Abstract: A decimation system comprising a plurality, L, of cascaded Finite Impulse Response (FIR) decimation filters. Each decimation filter has a transfer function of the form H(z)=(1+z?1)N, where N is an integer. Each FIR decimation filter performs decimation by a common factor I. The cascaded FIR decimation filters together achieve a decimation result substantially identical to that of an Nth-order CIC filter (that is, a CIC filter having N integrator stages) that performs decimation by a factor IL.

Abstract: A system for policing traffic of packet transfer in a hub. The system includes a first circuit and a second circuit and a first data line connecting the first circuit to the second circuit, wherein data is transmitted within and between the first circuit and the second circuit across said first data line. A second data line connects the first circuit to the second circuit, wherein data is transmitted within and between the first circuit and the second circuit across the second data line. A monitor monitors the first data line to determine when an amount of data being transmitted on the first data line within the first circuit has reached a threshold. A blocking mechanism prevents data from being transmitted on the first data line from the first circuit to the second circuit when the amount of data being transmitted on the first data line has reached the threshold.

Abstract: In a data communication system, a transmitter of an ADSL modem uses a PRBS generator to generate a plurality of ADSL signals. The transmitter computes the Peak to Average (e.g., root-mean-square) (“PAR”) ratio of each of the ADSL signals generated. The ADSL signal having the lowest PAR is determined, and the corresponding state of the PRBS generator is noted. The signal having the lowest PAR, or at least the corresponding state of the PRBS generator, is then used to generate a Q-mode signal.

Abstract: A network switch is disclosed having at least one data port interface for receiving data and at least one link interface configured to transmit the data between the network switch and other network switches. The switch contains a data processor, having a segmented ring with a plurality of dedicated modules designed to process the data connected through that ring. A programmable ring dispatcher dispatches at least a portion of the data along a segmented ring to at least one of the dedicated modules. The data processor also has a command processor for processing commands received from the dedicated modules. The programmable ring dispatcher determines the first dedicated module to receive the portion of the data and that first dedicated module thereafter determines the next destination for the data potion. Because the dedicated modules can be added to or taken out the switch architecture based on the network environment, the switch is scalable and adaptable.

Abstract: A capacitor including a first and second component capacitor structure disposed on a substrate. A component capacitor structure includes an upright arm, a transverse arm, and a via. The upright arm has a top end and a bottom end that extend at substantially right angles to a central axis of the upright arm. The transverse arm has a left and right end that extend at substantially right angles to a central axis of the transverse arm. The upright arm and the transverse arm intersect to form a cross-like pattern and the top, bottom, left and right ends all extend in the same rotary direction. The via is electrically coupled to an area of intersection of the upright and transverse arms.

Abstract: An improved dither generation circuit and method for digital audio circuits uses a high-pass filter to reduce the energy contained in the audio band of the dither signal. The resulting dither signal is applied to the circuit in its main feedback loop and is effective to prevent idle tones. Because of its spectrally shaped characteristic this dither signal introduces less noise into the audio band of interest and thereby improves the overall signal-to-noise ratio of the audio circuit. In an embodiment, the dither signal is generated using pseudo-random numbers that are then interpreted as 2's complement numbers.