Abstract: Methods and systems for extending the functionality of an embedded Universal Serial Bus (USB) transceiver interface to handle threshold shift of a USB 2.0 bus during high-speed chirp are presented. A method for a transceiver of a host coupled by a USB 2.0 bus to a device includes receiving a control signal, and selecting one of a first and second zero level voltage threshold according to the control signal. The first threshold is higher than the second to compensate for a shift in a zero level of the bus during high-speed chirp. In one example, the transceiver selects the first threshold when driving a reset signal, and selects the second threshold after detecting a device high-speed chirp signal. In another example, the transceiver selects the second threshold after driving a high-speed chirp sequence. In one example, the control signal includes a signal of a host controller embedded USB transceiver interface.

Abstract: A method, system, and apparatus for optimizing routing layers and board space requirements for a ball grid array land pattern is described. The land pattern includes a plurality of conductive pads arranged in an array of rows and columns. The array of pads has at least one edge of a perimeter of the array not fully populated with conductive pads, whereby spaces are created in the at least one edge by the missing conductive pads. The spaces create additional routing channels for signals from conductive pads within the array to be routed externally to the array through the at least one edge.

Abstract: An electrically and thermally enhanced die-up tape substrate ball grid array (BGA) package and die-up plastic substrate BGA package are described. A substrate that has a first surface and a second surface is provided. The stiffener has a first surface and a second surface. The second stiffener surface is attached to the first substrate surface. An IC die has a first surface and a second surface. The first IC die surface is mounted to the first stiffener surface. A plurality of solder balls is attached to the second substrate surface. In one aspect, a heat spreader is mounted to the second IC die surface. In another aspect, the stiffener is coupled to ground to act as a ground plane. In another aspect, the substrate has a window opening that exposes a portion of the second stiffener surface. The exposed portion of the second stiffener surface is configured to be coupled to a printed circuit board (PCB). In another aspect, a metal ring is attached to the first stiffener surface.

Abstract: This invention describes an apparatus and method to improve the performance of a decision feedback equalizer (DFE) for time-varying multi-path channels. For minimum-phase channels, the equalization is performed in a time-forward manner. For maximum-phase channels, the equalization is performed in a time-reversed manner. More specifically, for maximum-phase channels, the filter coefficients are computed based on the channel estimates reversed in time, and the filtering and equalization operations are performed with the received block of symbols in a time-reversed order. In the context of this invention, the term “minimum-phase channel” implies that the energy of the leading part of the channel profile is greater than the energy of the trailing part. The term “maximum-phase channel” implies that the energy of the leading part of the channel profile is less than the energy of the trailing part.

Abstract: A charge pump circuit includes a high-swing transconductance amplifier. A high input swing transconductance is provided in a negative feedback loop of the charge pump circuit without an abrupt change in transconductance. The high-swing transconductance amplifier includes a transconductance cell and high-swing circuitry. The transconductance cell includes a current supply transistor, which provides current for transconductance while input voltages are within the operational range for the transconductance cell. When the input voltages increase so as to be outside of the operational range, the current source transistor enters into triode region of operation, and provides reduced current. The high-swing circuitry supplies the current in this case so that abrupt change in transconductance does not occur.

Abstract: A method and system described for producing frequency multiplication/division by any non-integer output signal frequency relative to a reference signal frequency of a Phase Lock-Loop (PLL), while simultaneously maintaining low jitter. In one embodiment, the invention increases the number of the available clock phases to M and then shifts the output clock phase by one, every K/M cycle. In one aspect of the present invention, this is accomplished by adding a multiplexer (MUX) to the output of the PLL to implement the phase shifting every K/M cycles. In another aspect, the MUX is placed in the feedback loop of the PLL. In one embodiment, a quantizer is used to drive the MUX.

Abstract: A programmable divider includes a synchronous counter configured to process an input clock signal and produce first output signals in response the input clock signal. A number of logic devices are coupled to the synchronous counter and configurable to receive the first output signals and correspondingly produce second output signals. Also included is a multiplexer that is configured to receive the second output signals and has an output coupled to an input of the synchronous counter. In the programmable divider, characteristics of the synchronous counter are selectable based upon a particular number of the logic devices configured.

Abstract: Systems and methods that provide picture-in-picture timebase management are provided. In one example, a method may include the steps of sending a first video signal and a second video signal to a video decoder; sending a first audio signal to the audio decoder, the first audio signal being associated with the first video signal; locking a single timing mechanism to program clock references (PCRs) of the first audio signal; and decoding the first audio signal and the first video signal according to a timebase of the single timing mechanism.

Abstract: Portable measuring devices which communicate by low power transceivers through a communication controller with a printer device collect weight and size data on articles to be shipped. The collected weight and size data are combined with origin and destination data, and labels are printed bearing pertinent shipping and routing information in machine readable format. The labels are attached to the articles to be shipped and accompany the articles to their respective destinations. At transfer points the labels are read by scanner devices which also communicate by low power transceiver links with the communication controller. The wireless linking of the scanner devices promotes human safety by the absence of cords which could cause entanglement of an operator in mechanized conveying equipment. The communication controllers at each stage of the shipping process have the capability of transferring received and updated status information on the shipped articles to a central data station.

Abstract: System and method of data unit management in a decoding system employing a decoding pipeline. Each incoming data unit is assigned a memory element and is stored in the assigned memory element. Each decoding module gets the data to be operated on, as well as the control data, for a given data unit from the assigned memory element. Each decoding module, after performing its decoding operations on the data unit, deposits the newly processed data back into the same memory element. In one embodiment, the assigned memory locations comprise a header portion for holding the control data corresponding to the data unit and a data portion for holding the substantive data of the data unit. The header information is written to the header portion of the assigned memory element once and accessed by the various decoding modules throughout the decoding pipeline as needed. The data portion of memory is used/shared by multiple decoding modules.

Abstract: A high speed low power data transfer bus circuit that reduces bus power consumption by imposing a limited, controlled voltage swing on the associated data bus. In one embodiment, an inverter is coupled with a pMOS pass transistor and an nMOS discharge transistor, and the combination is coupled with a data bus. The discharge transistor and pass transistor can be programmed to provide a preselected bus operational characteristics. In another embodiment, multiple nMOS discharge transistors can be coupled to the data bus via the pass transistor, with each of the discharge transistors being selectively programmed to provide additional preselected bus operational characteristics, multiple, programmable discharge transistors, thus selectably imposing encoded and multilevel logic signals on the data bus. In another embodiment, a bidirectional data transfer bus circuit couples two data busses while imposing a limited, controlled voltage swing during the transfer.

Abstract: Certain embodiments of the present invention provides a system and method for SAP FM demodulation. The system includes a bandpass filter for isolating the SAP signal, a Hilbert filter to produce a copy of the SAP signal phase shifted by 90 degrees, an FM demodulator for demodulating the SAP signal using the phase shifted SAP signal and a delayed SAP signal, and a lowpass filter to eliminate noise from the FM demodulated SAP signal. The system may also include an automatic gain control for normalizing amplitude of FM demodulator input signals. The digital FM demodulator uses a simplified approximation using non-unity delay for simplified demodulation of frequency modulated signals.

Abstract: A method and system for allocating an initial maintenance request (IMR) for an upstream channel in a communications system, wherein the communication system includes a headend and at least one remote device associated with the channel. A first propagation delay from the headend to the remote device having the greatest delay is determined. Likewise, a second propagation delay from the headend to the remote device experiencing the least delay is determined. The IMR is then defined to be shorter than the first propagation delay and at least as long as the difference between the two propagation delays. The starting point of the IMR is established by modifying the clock output of the headend. A modification value is added to the headend clock output. The modification value corresponds to a time interval that can be as long as the propagation delay from the headend to the remote having the shortest delay.

Abstract: Methods and apparatus are provided for an entity such as a CPU to efficiently call a cryptography accelerator to perform cryptographic operations. A function call causes the cryptography accelerator to execute multiple cryptographic operations in a manner tailored for specific processing steps, such as steps during a handshake phase of a secured session. The techniques provide efficient use of hardware processing resources, data interfaces, and memory interfaces.

Abstract: A control terminal such as a CMTS is initialize to receive packets of voice calls having parameters including a bit rate, a packetization interval, and a call identification. A plurality of queues is created to define a corresponding plurality of phases at a sub-multiple of the packetization interval. Voice calls are admitted to the control terminal. The voice calls are distributed among the queues in a predetermined order as the voice calls are admitted and the voice calls removed from the queues as the voice calls are terminated. USGs are periodically issued at the phases defined by the queues. The USGs include a call identification and a grant of bandwidth sufficient to transmit the packets.

Abstract: An imaging device includes a plurality of photo-diodes that operate as optical pixels arranged in a plurality of columns on a single CMOS substrate. The outputs of the multiple pixel sensors, or photo-diodes, are examined to determine if a one pixel, or a region of pixels are in saturation. If so, then the pixel gain is adjusted to correct or compensate for the image distortion in the region. For example, the gain of the charging amplifier or operational amplifier can be adjusted to correct for saturation. This can be done in real-time since hardware is being tuned for the correction instead of software.

Abstract: Provided is a method and system for estimating distortion in a communications channel including an adaptive equalizer. The method includes determining one or more adaptive filter coefficients associated with a signal passed through the equalizer. The method also includes estimating un-equalized channel distortion based upon the determined adaptive filter coefficients.

Abstract: An apparatus includes a storage location and a write monitor circuit coupled to the storage location. The storage location is configured to store a write response indicator which is capable of indicating a reception of at least one write response. Each write response indicates that a corresponding write has reached a target device of that write. The write monitor circuit is configured to update the write response indicator in response to receiving an indication of a first write response. A computer accessible medium may comprises instructions which, when executed: (i) initialize the write response indicator; and (ii) issue one or more writes to a target device, wherein the target device is configured to response to each of the writes with a write response to be indicated by the write response indicator.

Abstract: Present herein is a low memory and MIPS efficient technique for decoding Huffman codes using multi-stage, multi-bits lookup at different levels. A binary tree is cut at levels depending on the quotient of the number of existing nodes and the number of possible nodes.

Abstract: System for measuring a thickness of a circuit component on a printed circuit board (PCB). The system includes a first circuit, a power plane, a power strip, a calibration strip, a temperature sensor, and a second circuit. The power plane is coupled to the first circuit. The power strip is for providing power to the power plane and is disposed in the PCB connected to the power plane. The power strip has at least two vias. The calibration strip has a predetermined width and is disposed in said PCB. The calibration strip has at least two vias for measuring a voltage drop. The temperature sensor is coupled to the calibration strip and configured to measuring a temperature of the calibration strip. The second circuit is coupled to the temperature sensor and configured to determine the thickness of the calibration strip based on at least the temperature of the calibration strip.