Abstract: Typical communication systems operate with a single channel decoder, and hence would have to settle for the performance from the single channel decoder regardless of the conditions of the communications channel. The present invention uses a hybrid channel decoder comprising multiple channel decoders, each configured to optimize the quality of the re-constructed signal for different channel conditions. Therefore, the desired decoder can be selected as conditions of the communications channel, or the data signal, change over time, so as to optimize the re-constructed data signal. In embodiments, the data signal is a speech signal.
Abstract: A method for determining differential delay of at least two bonded links is described. The method comprises a step of providing, on the part of a transmitting entity, at least some of the data packets transmitted from the transmitting entity to a receiving entity with time stamps, the time stamps indicating a point of time when a respective data packet has been generated, and a step of deriving a propagation delay from a time stamp of a data packet and a time of arrival of the data packet at a receiving entity. The method further comprises a step of determining a differential delay of a link from the propagation delay of the link and a propagation delay of a reference link.
Type:
Application
Filed:
June 9, 2005
Publication date:
December 29, 2005
Applicant:
Broadcom Corporation
Inventors:
Miguel Peeters, Raphael Cassiers, Benoit Christiaens
Abstract: A blanking interval information decoder is described, with the blanking interval decoder being adapted for decoding blanking interval information transmitted in a video signal. The blanking interval information decoder comprises a processing unit, a memory adapted for storing at least one of code and data, and a set of blanking interval decoding routines stored in the memory. Each of the blanking interval decoding routines is adapted for decoding a certain type of blanking interval information of a certain video standard.
Abstract: A tester unit for evaluating data integrity of a block of data is described. The tester unit comprises a checksum determination facility adapted for deriving a checksum value from a block of data stored in a memory, and a checksum evaluation facility adapted for comparing the derived checksum value with a predetermined checksum value, and for initiating a reload of the block in case the derived checksum value differs from the predetermined checksum value.
Abstract: The invention refers to a video data processing system and a video data processing circuit, comprising at least two functional blocks of which at least a first functional block is programmable so that different functions can be provided by said first functional block.
Abstract: A card includes in a radio transceiver that communicates in first and second frequency bands. First and second antennas are in the card and are coupled to the radio transceiver. A microprocessor in the card selects one of the first and second antennas.
Type:
Grant
Filed:
March 12, 2004
Date of Patent:
December 27, 2005
Assignee:
Broadcom Corporation
Inventors:
Patrick W. Kinney, Ronald L. Mahany, Guy J. West
Abstract: A method for enhancing the bit rate and/or margin at which quadrature amplitude modulation (QAM) communication is performed over multiple bands of a communication link includes the steps of varying a spectral allocation and constellation size with which communication is performed, so as to define a combination of spectral allocation and constellation size at which the bit rate and/or margin are enhanced. The rate adaptation method identifies the spectral allocation and constellation size to use on each of the multiple bands that results in a total bit rate greater than or equal to the target bit rate, subject to specified constraints on SNR margin and/or BER limits. If more than one parameter set has this property, the rate adaptation method may for example select the spectral allocation and constellation size combination that maximizes the minimum SNR margin across the multiple bands.
Abstract: A signal processing system which discriminates between voice signal and data signals modulated by a voiceband carrier. The signal processing system includes a voice exchange, a data exchange and a call discriminator. The voice exchange is capable of exchanging voice signals between a switched circuit network and a packet based network. The signal processing system also includes a data exchange capable of exchanging data signals modulated by a voiceband carrier on the switched circuit network with unmodulated data signal packets on the packet based network. The data exchange is performed by demodulating data signals from the switched circuit network for transmission on the packet based network, and modulating data signal packets from the packet based network for transmission on the switched circuit network. The call discriminator is used to selectively enable the voice exchange and data exchange.
Type:
Grant
Filed:
October 26, 2000
Date of Patent:
December 27, 2005
Assignee:
Broadcom Corporation
Inventors:
Wilf LeBlanc, Shawn Stevenson, Wing Yee Winnie Lee
Abstract: A network device including at least one network port, a clock, address resolution logic (ARL) tables, and address resolution logic. The clock generates a timing signal. The ARL tables are configured to store and maintain data related to port addresses of the network device. The address resolution logic is coupled to the ARL tables and the clock, and configured to search the ARL tables and to perform learning concurrently during alternating slots of the timing signal. Upon receiving a data packet at the at least one port, the address resolution logic is configured to search the ARL tables for a destination address based on the data packet. When the destination address is found, the address resolution logic is configured to update a related record of the ARL tables based on the learning, the address resolution logic configured to perform searches and updates.
Abstract: A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a descriptor-based packet processing mechanism for use in efficiently assigning and processing packets to a plurality of processors. A plurality of descriptors associated with each packet transfer are written back to memory in order, divided into subset groups and assigned to processors, where each processor searches the assigned subset for EOP and associated SOP descriptors to process.
Abstract: A system and method for noise cancellation in a signal-processing circuit (e.g., an analog-to-digital converter circuit). Various aspects of the present invention may comprise inputting a first input signal and a digital input signal to the signal-processing circuit. The digital input signal may, for example, comprise a digital dither signal or other processor control signal. The signal-processing circuit may, for example, output a signal comprising a first signal component that is primarily a function of the first input signal and a second signal component that is primarily a function of the digital input signal. The second signal component may be estimated based on estimated behavior of the signal-processing circuit in response to the digital input signal. The estimated second signal component may, for example, be substantially removed from the signal-processing circuit output signal.
Abstract: A method of searching a plurality of Vector Quantization (VQ) codevectors for a preferred one of the VQ codevectors to be used as an output of a vector quantizer for encoding a speech signal, includes determining a quantized prediction residual vector, and calculating a corresponding unquantized prediction residual vector and the energy of the difference between these two vectors (that is, a VQ error vector).
Abstract: A method and apparatus for adaptively controlling a variable gain amplifier (VGA). The operation of the VGA is separated into a low gain mode and a high gain mode and the mode in which the VGA is currently operating in is adaptively sensed. A threshold voltage is compared to a control voltage of the VGA; if the VGA is currently operating in the low gain mode and the control voltage is higher than the threshold voltage, the VGA is switched from the low gain mode to the high gain mode; and if the VGA is currently operating in the high gain mode and the control voltage is lower than the threshold voltage, the VGA is switched from the high gain mode to the low gain mode.
Abstract: The motherboard comprises a CPU and a memory component; further at least one video data processing chip mounted to the motherboard wherein the video data processing chip is programmable; and further at least one additional memory component provided to store a software that is executable by the video data processing chip.
Abstract: An RF MOS transistor having improved AC output conductance and AC output capacitance includes parallel interdigitated source and drain regions separated by channel regions and overlying gates. Grounded tap regions contacting an underlying well are placed contiguous to source regions and reduce distributed backgate resistance, lower backgate channel modulation, and lower output conductance.
Abstract: A system, device and method are disclosed for predicting the opacity of primitives used to produce an image using one or more equations, prior to producing an image. More specifically, the present invention relates to a 3D device adapted to produce an image comprising an opacity estimate predictor adapted to predict opacity of at least one primitive using at least one first equation and further adapted to reject the primitive if the predicted opacity is equal to a minimum value.
Abstract: One or more methods and systems of validating the operation of one or more register designs are presented. In one embodiment, the system utilizes a processor, an integrated circuit design simulator software, a storage media, a storage device, user interface, and a display. In one embodiment, the method includes executing a set of instructions operating on a register design parameter file to produce an output that is easily incorporated into the integrated circuit design simulator software. The output specifies one or more tests to be performed using the integrated circuit design simulator software. The one or more tests are subsequently performed to validate the register design. The method automates the incorporation of register design parameters into the integrated circuit design simulator software by way of executing a set of instructions that operates on the register design parameter file.
Abstract: A low-error fixed-width multiplier receives a W-bit input and produces a W-bit product. In an embodiment, a multiplier (Y) is encoded using modified Booth coding. The encoded multiplier (Y) and a multiplicand (X) are processed together to generate partial products. The partial products are accumulated to generate a product (P). To compensate for the quantization error, Booth encoder outputs are used for the generation of error compensation bias. The truncated bits are divided into two groups, a major least significant bit group and a minor least significant bit group, depending upon their effects on the quantization error. Different error compensation methods are applied to each group.
Type:
Grant
Filed:
August 30, 2002
Date of Patent:
December 20, 2005
Assignee:
Broadcom Corporation
Inventors:
Keshab K. Parhi, Jin-Gyun Chung, Kwang-Cheol Lee, Kyung-Ju Cho
Abstract: A squeezable tail current source for use in a differential operational amplifier is disclosed that regulates the current through a main input differential pair while preventing output distortion and allowing high linearity. The squeezable tail current source includes a first transistor pair that replicates a main input transistor pair, wherein both the first transistor pair and the main input transistor pair receive a common voltage input at their respective gates. The squeezable tail current source also includes a second transistor pair, a bias transistor, a first current source, a folding transistor, and a second current source that biases the folding transistor. These components are configured such that current through the main input transistor pair is maintained as the voltage input varies.
Abstract: A method for controlling a video stream bit rate while encoding a macroblock of a video stream having pictures comprising the step of using a quantiser_scale_code of the general form: quantiser—scale—code=ROUND(A+B(D+logC(MIN{VAR[luma—0], . . . ,VAR[luma—n]}))) with A being an adjustable gear shift parameter; and B being an adjustable gas pedal parameter; and [luma_n] being a nth luminance block of said macroblock; and D being a constant parameter depending on the encoded picture type.