Patents Assigned to Broadcom Corporations
-
Publication number: 20050270203Abstract: In a high-fidelity digital modulator, a mapper is provided to minimize quantization noise, jitter, and cross-talk between multiple digital-to-analog or analog-to-digital converters. The mapper receives a quantized level from a quantizer and maps the quantized level to an output sequence. The mapper includes a table defining multiple sequences corresponding to each quantized level. Each sequence includes two or more symbols, having one of multiple values. The mapper also includes a generator that selects one of the multiple sequences as the output sequence. The last symbol of a first output sequence is equal to the first symbol of the next output sequence and so on. The generator selects the output sequence by alternating between a first and a second sequence for each quantized level received. The generator selects the output sequence by alternating between sequences having a positive and a negative common mode energy for each odd valued quantized level received.Type: ApplicationFiled: May 9, 2005Publication date: December 8, 2005Applicant: Broadcom CorporationInventors: Todd Brooks, Kevin Miller, Josephus Van Engelen
-
Publication number: 20050273582Abstract: The present invention relates to a design of a computer system that processes instructions with a specific operation code causing the processor to execute a certain operation twice and a method for running such computer system in a time and register space saving manner. A method is provided for executing at least one computer instruction which defines at least a first source operand and an operation to be carried out on the operand, the instruction containing at least one address field of a predetermined bit length and at least one repeated execution bit related to the first operand. The method includes accessing the first source operand; accessing the repeated execution bit and deriving from that repeated execution bit a repeated execution code defining a repeated execution condition; and selectively carrying out the operation defined in the instruction once, twice or more times in dependence of the repeated execution code.Type: ApplicationFiled: June 2, 2004Publication date: December 8, 2005Applicant: Broadcom CorporationInventor: Sophie Wilson
-
Publication number: 20050273533Abstract: The invention refers to a computer system, comprising: a computer, and a peripheral device, wherein the computer comprises one or more receivers for receiving signals sent from the peripheral device, and a peripheral device movement detector for detecting a movement of the peripheral device from the signals received from the peripheral device. Further, the invention referes to a mobile telephone, comprising a device movement tracking member, e.g., a rollerball. In addition, the invention refers to a computer system, comprising: a mobile telephone comprising a device movement tracking member, and a computer connectable to the mobile telephone, e.g. via a wireless RF connection.Type: ApplicationFiled: June 7, 2005Publication date: December 8, 2005Applicant: Broadcom CorporationInventor: Peter Hughes
-
Publication number: 20050270210Abstract: A system and method for an improved analog front-end system is disclosed. By coupling a switch to the output of a track-and-hold circuit and to the input of a time-discrete circuit, such as an analog-to-digital converter, the time-discrete circuit can be disconnected from the track-and-hold circuit during the track mode of the track-and-hold circuit. This improved system reduces the load of the T/H circuit from the full input capacitance of the time-discrete circuit to the smaller parasitics of the switch thereby providing a T/H circuit with lower power consumption and smaller area while maintaining high speed and high accuracy.Type: ApplicationFiled: June 2, 2004Publication date: December 8, 2005Applicant: Broadcom CorporationInventor: Erol Arslan
-
Patent number: 6972625Abstract: Continuously tuning a transconductance. Coupling a degeneration resistance from a first source of a first transistor in a differential pair of transistors to a second source of a second transistor in the differential pair of transistors. Applying a second variable degeneration resistance in parallel to the first degeneration resistance in response to the application of a first variable control voltage. And applying a third variable degeneration resistance in parallel to the first degeneration resistance and the second degeneration resistance in response to the application of a second variable control voltage having a fixed voltage offset from the first variable control voltage.Type: GrantFiled: April 14, 2004Date of Patent: December 6, 2005Assignee: Broadcom CorporationInventors: Thinh Cat Nguyen, Arnoldus Venes
-
Patent number: 6972616Abstract: A low-noise, fast-settling bias circuit includes a first and a second low pass filter, such as RC filters. The second filter initially shorts out a resistor of the first filter with a switch (set to low impedance) in parallel. Accordingly, a capacitor of the first filter quickly charges up to the same voltage as the input bias voltage. As the second filter charges up, the switch slowly shuts off (high impedance). By this time, since the capacitor of the first filter has charged to the same voltage as the bias voltage, a large RC formed by the resistor of the first filter and the capacitor of the first filter is available to provide filtering for the desired bias current.Type: GrantFiled: April 14, 2004Date of Patent: December 6, 2005Assignee: Broadcom CorporationInventor: Stephen Wu
-
Patent number: 6972610Abstract: An RF communications system includes a transmit node for transmitting an RF information signal and a receive node for receiving the transmitted RF information signal. The receive node includes a passive mixer coupled to an amplifier for producing an IF or baseband differential mixer output signal as a function of a LO drive signal. The passive mixer having a first plurality of transistors of a first polarity type arranged in a ring configuration and a second plurality of transistors of a second polarity type, wherein each of second plurality of transistors is coupled to one of the first plurality of transistors.Type: GrantFiled: November 17, 2004Date of Patent: December 6, 2005Assignee: Broadcom CorporationInventor: Arya Reza Behzad
-
Patent number: 6972629Abstract: A power amplifier includes a transconductance stage and a modulation detection and bias determination module, and may include a cascode stage. The modulation detection and bias determination module operably couples to the transconductance stage and to the cascode stage when present and is operable to detect modulation characteristics of an signal operated upon by the transconductance stage. The modulation detection and bias determination module is also operable to controllably bias the transconductance stage and/or the cascode stage when present based upon detected modulation characteristics. The detected modulation characteristics are typically determined based upon a measured signal level, e.g., voltage level, current level, or power level, of the signal operated upon by the transconductance device. For non-constant envelope modulations, the signal level varies over time with the modulation envelope. The operational characteristics of the power amplifier, e.g.Type: GrantFiled: March 12, 2004Date of Patent: December 6, 2005Assignee: Broadcom CorporationInventor: Arya Reza Behzad
-
Patent number: 6973094Abstract: A packet-switched multiple-access network system with a distributed fair priority queuing media access control protocol that provides multiple levels of priority of access and fair collision resolution with improved performance is disclosed. In one embodiment, the system provides high-speed transport of multimedia information on a shared channel. Further, in one embodiment, MAC level side-band signaling that is useful to other levels of the network protocol (e.g., the physical layer) is also provided.Type: GrantFiled: September 29, 2000Date of Patent: December 6, 2005Assignee: Broadcom CorporationInventors: John T. Holloway, Jason Trachewsky, Henry Ptasinski
-
Patent number: 6972556Abstract: A system for measuring power of a circuit on a printed circuit board (PCB) including first and second circuits, a power strip, a power plane, and a calibration strip. The power strip is connected to the power plane to the first circuit, is embedded in the PCB during the manufacturing process, and also has at least two vias for measuring a voltage drop. The calibration strip is also embedded in the PCB during the manufacturing process and has at least two vias for measuring a voltage drop. The second circuit is configured to measure a voltage drop across the power strip as a first voltage and a voltage drop across the calibration strip as a second voltage, and to calculate the power being fed to the first circuit based on the first voltage and the second voltage.Type: GrantFiled: July 20, 2004Date of Patent: December 6, 2005Assignee: Broadcom CorporationInventors: James M. Kronrod, James J. Freeman, Kelly Coffey
-
Patent number: 6973058Abstract: According to the present invention, simultaneous call-handling and data transfer is achieved between a terminal and a multi-line gateway in a cordless telephony environment. Multiple logical channels are established and used as signaling resources for calls on the multiple lines, and also for data transfers between the gateway and terminal. As a result, terminals can handle multiple calls on different lines and at the same time access data stored at the gateway. According to a first aspect of the present invention, two or more logical channels are established over an asynchronous channel between a terminal and a gateway. These logical channels are assigned to calls that are set-up between the terminal and gateway. When used as a signaling resource, the logical channels allow the terminal to distinguish between signaling information for multiple simultaneous calls. The calls are associated with another speech or data channel that will bear the voice signal, referred to herein as a bearer channel.Type: GrantFiled: July 31, 2001Date of Patent: December 6, 2005Assignee: Broadcom CorporationInventor: Harish P. Paryani
-
Publication number: 20050264357Abstract: A biasing scheme for a MOSFET that mitigates the MOSFET body effect. The biasing scheme can be realized replicating the voltage at the source terminal of a MOSFET and applying this replicated voltage to the body terminal. In this manner, the effect of the body transconductance, at high frequencies, becomes a function of the ratio of the well-to-substrate capacitance of the MOSFET to the sum of the well-to-substrate capacitance and the source-to-body capacitance of the transistor. At high frequencies, the biasing scheme mitigates the reduction in gain of a source follower caused by the body effect of a driven MOSFET within the source follower, improves the stability of a feedback network established by a gain boosting amplifier and the driven MOSFET by contributing a negative half plane zero to the transfer function of the feedback network, and reduces the power consumed by the gain boosting amplifier.Type: ApplicationFiled: May 6, 2005Publication date: December 1, 2005Applicant: Broadcom CorporationInventor: Sandeep Gupta
-
Publication number: 20050265446Abstract: A system and method for detecting and reducing mosquito noise are disclosed. Areas within a frame with mosquito noise are detected by calculating the variance of the luminance blocks in a macroblock, determining the minimum variance of the macroblock luminance blocks, and comparing the minimum variance to a mosquito noise threshold. If the minimum variance is greater than the mosquito noise threshold, then the macroblock is considered a high activity macroblock and the corresponding macroblock bit in the frame bitmap is set. If the minimum variance is less than or equal to the mosquito noise threshold, then the macroblock is considered a low activity macroblock, and the corresponding macroblock bit in the frame bit map is cleared. If the current macroblock bit is set in the corresponding frame bitmap or if at least one of its adjacent eight macroblock bits is set in the corresponding frame bitmap, then the current macroblock requires mosquito noise reduction.Type: ApplicationFiled: August 20, 2004Publication date: December 1, 2005Applicant: Broadcom CorporationInventor: Itzik Yankilevich
-
Publication number: 20050264344Abstract: A power-down biasing circuit including a current source connected to a drain of a first NMOS transistor through a first switch. A gate of the first NMOS transistor is connected to the current source, and a source of the first NMOS transistor is connected to ground. A first capacitor connected between the gate of the first NMOS transistor and ground. A plurality of NMOS transistors form a current multiplier and have gates connected to the current reference. A plurality of current mirrors are connected to drains of the plurality of NMOS transistors and to output switches.Type: ApplicationFiled: May 27, 2004Publication date: December 1, 2005Applicant: Broadcom CorporationInventors: Kwang Kim, Josephus van Engelen
-
Patent number: 6971006Abstract: An architecture and a method for a cryptography acceleration is disclosed that allows significant performance improvements without the use of external memory. Specifically, the chip architecture enables “cell-based” processing of random-length IP packets. The IP packets, which may be of variable and unknown size, are split into fixed-size “cells.” The fixed-sized cells are then processed and reassembled into packets. The cell-based packet processing architecture of the present invention allows the implementation of a processing pipeline that has known processing throughput and timing characteristics, thus making it possible to fetch and process the cells in a predictable time frame. The architecture is scalable and is also independent of the type of cryptography performed. The cells may be fetched ahead of time (pre-fetched) and the pipeline may be staged in such a manner that attached (local) memory is not required to store packet data or control parameters.Type: GrantFiled: August 23, 2002Date of Patent: November 29, 2005Assignee: Broadcom CorporationInventors: Suresh Krishna, Christopher Owen
-
Patent number: 6970689Abstract: A state of a programmable mixer is set during a calibration phase to minimize local oscillator feedthrough. During a calibration phase, inputs to the programmable mixer are set to zero, or to a known state and the local oscillator is set to a calibration frequency. Then, one of a plurality of known calibration states of the programmable mixer is entered and the local oscillator feedthrough is measured. For each of a plurality of operating states an amplified output of the programmable mixer is measured. In one operation, the state of the programmable mixer in which the programmable mixer operates during a next operation phase is the state that produces minimal local oscillator feedthrough. In another operation, operation continues until a state is found that produces a local oscillation feedthrough that meets an operating criteria and that state is used during the next operation phase.Type: GrantFiled: April 3, 2002Date of Patent: November 29, 2005Assignee: Broadcom CorporationInventor: Shahla Khorram
-
Patent number: 6970434Abstract: A hierarchical communication system, arranged in a spanning tree configuration, is described in which wired and wireless communication networks exhibiting substantially different characteristics are employed in an overall scheme to link portable or mobile computing devices. Copies of data, program code and processing resources are migrated from their source toward requesting destinations based on request frequency, communication link costs and available local storage and/or processing resources. Each appropriately configured network device acts as an active participant in network migration. In addition, portable two-dimensional (2-D) code reading terminals are configured to wirelessly communicate compressed 2-D images toward stationary access servers that identify the code image through decoding and through comparison with a database of images that have previously been decoded and stored.Type: GrantFiled: August 4, 1998Date of Patent: November 29, 2005Assignee: Broadcom CorporationInventors: Ronald L. Mahany, Guy J. West, Alan G. Bunte, Arvin D. Danielson, Michael D. Morris, Robert C. Meier
-
Patent number: 6970382Abstract: In a digital memory system, systems and methods that control a logical value and an integrity of data represented by charge are provided. In one embodiment, a bit line is coupled to the cell. A voltage generator is arranged to generate a plurality of cell operating voltages varying in response to a voltage control signal. A controller generates a control signal, stores a predetermined one of logical values in a cell by generating a series of operating voltages, transmits the series of operating voltages, and determines whether the predetermined one of the logical values has been stored in the cell in response to a voltage on the bit line. The controller includes a charge integrity estimating module and determines whether the predetermined one of the logical values has been stored in the cell by initiating the operation of the charge integrity estimating module.Type: GrantFiled: December 29, 2004Date of Patent: November 29, 2005Assignee: Broadcom CorporationInventors: Zeynep Toros, Esin Terzioglu, Ahmad O. Siksek, Gil I. Winograd, Ali Anvar
-
Patent number: 6971033Abstract: A method and apparatus are disclosed for performing dynamic arbitration of memory accesses by a CPU and at least one bus master interface module based on, at least in part, monitoring a CPU throttle control signal and monitoring CPU power and performance states, and making decisions based on the monitored parameters. Bus master memory access break events and memory read and write accesses are also monitored as part of the arbitration process in accordance with certain embodiments of the present invention. An arbitration (ARB) module performs the dynamic arbitration. A CPU throttle control module generates the CPU throttle control signal, indicating when the CPU is idle, and also monitors and outputs the CPU power and performance states. A memory controller (MC) module controls accesses to the memory subsystem based on, at least in part, the dynamic arbitration performed by the dynamic arbitration module.Type: GrantFiled: January 10, 2003Date of Patent: November 29, 2005Assignee: Broadcom CorporationInventor: Kenneth Ma
-
Patent number: 6971038Abstract: A processor may include an execution circuit, an issue circuit coupled to the execution circuit, and a clock tree for clocking circuitry in the processor. The issue circuit issues an instruction to the execution circuit, and generates a control signal responsive to whether or not the instruction is issued to the execution circuit. The execution circuit includes at least a first subcircuit and a second subcircuit. A portion of the clock tree supplies a plurality of clocks to the execution circuit, including at least a first clock clocking the first subcircuit and at least a second clock clocking the second subcircuit. The portion of the clock tree is coupled to receive the control signal for collectively conditionally gating the plurality of clock, and is also configured to individually conditionally gate at least some of the plurality of clocks responsive to activity in the respective subcircuits of the execution circuit.Type: GrantFiled: February 1, 2002Date of Patent: November 29, 2005Assignee: Broadcom CorporationInventors: Sribalan Santhanam, Vincent R. von Kaenel, David A. Kruckemyer