Abstract: A video data processing device, such as a set-top box for satellite, DSL, or cable video and data services, has a USB 2.0 interface to support connections to local devices and networks. The interface is supported by drivers that provide data connectivity with the internal system bus of the data processing device, to support wired and/or wireless home networking with computers and other set-top boxes, data storage and retrieval on hard drives and other storage media, and other data transfer operations to support digital cameras, game ports, and printers.

Abstract: A system and method are disclosed for efficiently determining a prediction block for a current block of interest in a video signal encoding protocol. In a preferred embodiment, this is achieved by determining whether there is a correlation between the intra 4×4 predictions and the 16×16 prediction modes. If the correlation to the 16×16 prediction modes is lower than a predetermined threshold value, then the additional prediction blocks using 16×16 intra luma prediction are not calculated. If the correlation to the 16×16 prediction modes is higher than the predetermined threshold value, then the additional prediction blocks are calculated using 16×16 intra luma prediction. A cost function may then be used to determine the predicted bit cost of each prediction block, and the prediction block with the lowest cost may be selected as the prediction block for the current block of interest.

Abstract: A method and system, compatible with low-voltage CMOS technology, for controlling the charging of a battery. The method includes monitoring a battery voltage with respect to a threshold voltage. The method further includes coupling a charging control logic supply to ground, generating an active low first control signal, inverting the active low first control signal, and charging the battery at a first rate when the battery voltage is below the threshold voltage. The method further includes coupling the charging control logic supply to the battery voltage, generating an active high second control signal, and charging the battery at a second rate when the battery voltage exceeds the threshold voltage. The first charging rate is slower than the second charging rate. The method further includes supplying battery power to a charger line when the battery voltage exceeds the charger voltage, and suppressing a leakage current.

Abstract: A system and method for removing impulsive noise from a digital signal are disclosed. The system and method determines either a neighborhood maximum and/or a neighborhood minimum for a pixel of interest. The intensity of the pixel of interest is then compared to the neighborhood maximum or the neighborhood minimum to determine whether the pixel of interest should be replaced.

Abstract: A processing pipeline with a plurality of pipeline stages is described, with the processing pipeline comprising a front end and a back end. The processing pipeline's front end comprises an array for storing at least two condition bits, said condition bits being adapted for indicating respective conditions. The front end is adapted for resolving conditional branch instructions by accessing said array of condition bits whenever a conditional branch instruction occurs, the respective branch instruction being resolved in accordance with a corresponding condition bit. In another embodiment, the condition bits are combined with predicated execution of instructions, with the instruction's predicates being evaluated at the processing pipeline's back end.

Abstract: A radio transceiver includes a charge pump formed within a local oscillator that adjusts a voltage input to a voltage-controlled oscillator in a manner that flattens a response curve for small changes in voltage due to a variety of effects including channel length modulation. Thus, a local oscillation tends to provide a greater degree of stability. More specifically, the charge pump of the transceiver includes a pair of feedback circuits that source an additional amount of current into a filter to slightly increase a voltage input to the voltage-controlled oscillator in response to small upward changes in output voltage levels (input with respect to the voltage-controlled oscillator). Similarly, when the output voltage level drops slightly, a second feedback circuit causes a small amount of current to be sinked from the output node thereby slightly decreasing the input voltage to the voltage-controlled oscillator.

Abstract: A method of and device for performing a data expansion operation on a plurality of input data objects to generate expanded output data objects is disclosed. The method comprises receiving and decoding a data manipulation instruction defining a data expansion operation, a portion of the data manipulation instruction indicating an expansion operation from a number of predetermined types of data manipulation operations. The method includes generating one or more expansion objects responsive to the indication of an expansion operation, said expansion objects being for use in extending an input data object. The input data objects and said expansion objects are manipulated according to control information programmed to produce a set of expanded output data objects.

Abstract: A system and method are used to allow high speed communication between a chip and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circuitry to interface circuitry, and a phase interpolated voltage controlled delay line configured to phase shift incoming signals. Analog design techniques of phase interpolation accurately position clocks and strobe signals that are required for high speed interfaces. The high speed interface is for transmitting and receiving signals from the external device, for example, a DDR DRAM.

Abstract: A method of controlling data sampling clocking of asynchronous network nodes, each asynchronous network node having a local clock and transmitting and receiving packets to and from an asynchronous network according to an asynchronous network media access protocol. An asynchronous network node capable of transmitting and receiving packets on the asynchronous network is designated as a master node. Each non-master asynchronous network node which desires to synchronously transport packets across the asynchronous network is designated as a slave node. A master node clock of the master node is synchronized with a slave node clock of each slave node. Each slave node clock is continuously corrected compared with the master node clock to smooth slave clock error to an average of zero compared with the master clock as a reference using timestamp information from the master node.

Abstract: A method and system that allows the distribution of hot spare space across multiple disk drives that also store the data and redundant data in a fully active array of redundant independent disks, so that an automatic rebuilding of the array to an array of the identical level of redundancy can be achieved with fewer disk drives. The method configures the array with D disk drives of B physical blocks each. N user data and redundant data blocks are allocated to each disk drive, and F free blocks are allocated as hot spare space to each disk drive, where N+F<=B, and ((D?M)×F)>=N. Thus, rebuilding of data and redundant blocks of a failed disk drive in the free blocks of the remaining disk drives is enabled after M disk drive failures.

Abstract: An apparatus for a processor includes a first scoreboard, a second scoreboard, and a control circuit coupled to the first scoreboard and the second scoreboard. The control circuit is configured to update the first scoreboard to indicate that a write is pending for a first destination register of a first instruction in response to issuing the first instruction into a first pipeline. The control circuit is configured to update the second scoreboard to indicate that the write is pending for the first destination register in response to the first instruction passing a first stage of the pipeline. Replay may be signaled for a given instruction at the first stage. In response to a replay of a second instruction, the control circuit is configured to copy a contents of the second scoreboard to the first scoreboard. In various embodiments, additional scoreboards may be used for detecting different types of dependencies.

Abstract: A memory management system provides the ability for multiple requesters to access blocks of memory in a pipelined manner. During a first clock, requests for one or more of the memory blocks are received by the system. A determination is made of whether one of the memory blocks is requested by one or more requests. If the same memory block is requested by two or more requests, the system performs a further determination of which of the requests will be provided to the memory block. The determined request is provided to the memory block on the first clock. During a second clock, the data of the determined request is latched to the memory block and a memory access is initiated. If the request is a write request, the data is written to the memory block. If the request is a read request, then the requested data is retrieved and, on a third clock, the data is driven onto a bus, routed to the determined requester, and available to be latched into the requester on the fourth clock.

Abstract: An integrated Ethernet PHY/MAC apparatus having a single link partner capability register shared between a PHY and a corresponding MAC, which implements IEEE Standard 302.3, including IEEE Standards 802.3u and 802.3x. Apparatus also includes plural PHYs, each having a corresponding MAC integrably coupled therewith such that an integrated multi-port Ethernet device is realized. A network consists of at least one integrated Ethernet PHY/MAC device having a single link partner capability register.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: A scaled input current is produced that substantially matches the full scale input of a CT??ADC that substantially cancels an offset bias current component of the input current. A variable bias resistance value is coupled between the integrator input and one of a supply voltage and a circuit common. The method further includes integrating the input current to produce an integrated signal representing a time averaged value of the input current to substantially remove noise from a frequency band of interest. The integrated signal is produced to a quantizer to produce a feedback current that substantially cancels a quantization noise component in the digital representation of the scaled analog signal by coupling the digital representation of the scaled analog signal to a programmable digital switch wherein the programmable digital switch either sinks current from or sources current to the integrator input.

Abstract: A video and graphics system includes a data transport processor for receiving compressed data streams, a video transport processor for extracting video data, and an audio decode processor for extracting audio data. The data transport processor provides PCRs to the video transport processor and the audio decode processor. The video transport-processor stores the video data in external memory and generates a start code table to index the video data stored the external memory. In the start code table SLICEs of the video data are aligned to a suitable boundary. The compressed data streams may include MPEG Transport streams, and the video data may include SDTV or HDTV data. The video and graphics system may be implemented on an integrated circuit chip.

Abstract: The present invention relates to the field of (micro)computer design and architecture, and in particular to microarchitecture associated with moving data values between a (micro)processor and memory components. Particularly, the present invention relates to a computer system with an processor architecture in which register addresses are generated with more than one execution channel controlled by one central processing unit with at least one load/store unit for loading and storing data objects, and at least one cache memory associated to the processor holding data objects accessed by the processor, wherein said processor's load/store unit contains a high speed memory directly interfacing said load/store unit to the cache. The present invention improves the of architectures with dual ported microprocessor implementations comprising two execution pipelines capable of two load/store data transactions per cycle.

Abstract: The invention refers to an electronic system, comprising several power-dissipating components, and a circuit board, wherein said power-dissipating components are mounted both to a top side and a bottom side of said circuit board. Further, the invention refers to method for mounting power-dissipating components onto a circuit board, comprising the steps of (a) determining the thermal behavior of said power-dissipating components; and (b) determining, in accordance thereto, the placement of said power-dissipating components on both a top side and a bottom side of said circuit board.

Abstract: The present invention relates to the field of (micro)computer design and architecture, and in particular to microarchitecture associated with moving data values between a (micro)processor and memory components. Particularly, the present invention relates to a computer system with an processor architecture in which register addresses are generated with more than one execution channel controlled by one central processing unit with at least one load/store unit for loading and storing data objects, and at least one cache memory associated to the processor holding data objects accessed by the processor, wherein said processor's load/store unit contains a high speed memory directly interfacing said load/store unit to the cache and directly accessible by the cache memory for implementing scatter and gather operations. The present invention improves the performance of architectures with dual ported microprocessor implementations comprising two execution pipelines capable of two load/store data transactions per cycle.

Abstract: A system and method for optimizing the power level in the upstream direction in an ADSL communication system are disclosed. The system and method optimize the upstream signal power level by determining at least one system parameter related to the transmission of the input communications signal and modifying the bit and gain tables in response to the system parameter to optimize the upstream power level. More specifically, in one embodiment, the present invention selects a maximum received power configuration parameter for a receiving device, measures the received signal power at the receiving device, determinines a power backoff parameter for the transmitting device, uses the power backoff to modify the bit and gain tables and communicates the modified bit and gain tables to the transmitting device.