Abstract: Techniques and devices provide analog-to-digital conversion at two or more signal frequencies or frequency bands and can be used to construct multi-mode analog-to-digital converters in various circuits, including receivers and transceivers for wireless communications and radio broadcast environments. Adjustable analog-to-digital converters based on the described techniques can be configured to adjust circuit parameters to adapt the technical specifications of different input signals at different signal frequencies or frequency bands, such as FM, HD-radio, and DAB radio signals in radio receiver applications.

Abstract: Methods, systems, and computer program products for enhancing transmitted audio signals for a video conference call are disclosed. Facial recognition technology and audio processing techniques determine a position of a speaking member of a party on a video conference. Based on the determined position of the speaking member, the directionality of the received audio signals can be adjusted towards the speaking member. The video conference system can transmit the adjusted audio signals.

Abstract: Embodiments of a radio frequency (RF) receiver implementing one or more forms of protection to protect devices of the RF receiver from in-band interferers is provided. The RF receiver includes an integrated circuit terminal configured to couple a RF signal received at an antenna to a RF signal path, and a low noise amplifier (LNA) coupled to the RF signal path and configured to amplify the RF signal to provide an amplified RF signal. To protect the LNA from in-band interferers, the RF receiver can further include one or more clamping circuits and/or an over-voltage detector to determine if a peak of the RF signal exceeds an acceptable level.

Abstract: Embodiments of the present invention provide systems and methods to enable secure communication between a host processor and external real time counter (RTC) logic. In an embodiment, the host processor generates a message including a command to an external device containing the RTC. The external device verifies a Message Authentication Code (MAC) included in the message and responds to the command. Embodiments of the present invention advantageously provide a dedicated power domain for the external RTC logic while guarding against third party attacks on the RTC logic and the communication between the RTC logic and the host processor.

Abstract: A technique to use a two-step calibration procedure to calibrate a voltage controlled oscillator (VCO) of a phase-locked loop. The first calibration step is an open-loop calibration procedure in which a control voltage of the VCO is temperature compensated and the VCO is tuned using a search routine to generate a corresponding output frequency based on the control voltage. The second step is a closed-loop calibration procedure to adjust the tuning components of the VCO to correct for a 1 LSB error.

Abstract: According to one embodiment, a high performance buffer for use in a communications system includes first and second differential blocks. Each of the first and second differential blocks comprise one or more driving transistors for generating a driving current for a load of the high performance buffer, and a feedback path for adjusting the operation of the one or more driving transistors. The feedback path includes a feedback transistor for receiving a common mode bias voltage, wherein the common mode bias voltage depends at least in part on a threshold voltage of the feedback transistor. The feedback path includes a programmable resistor and capacitor to reduce out of band loop gain and the noise. The high performance buffer is configured to achieve a high linearity, low output impedance, and low noise, and is suitable for use as a pre-mixer buffer in a wireless communications system.

Abstract: A system and method for increasing input/output speeds in a network switch. A physical layer device is provided that includes a physical coding sublayer that insert data flow identifiers to data flows that are provided to a gearbox. In one embodiment, the gearbox is a 5 to 2 gearbox that can transport various combinations of 10G/40G data flows over a narrower interface to a second physical layer device having an inverse gearbox.

Abstract: Methods, devices, systems and computer program products are provided to facilitate cryptographically secure retrieval of secret information that is embedded in a device. The embedded secret information can include a random number that is not custom-designed for any specific requestor of the secret information. Upon receiving a request for the embedded secret information, an encrypted secret is provided to the requestor that enables the recovery of the embedded secret information by only the requestor. Moreover, a need for maintenance of a database of the embedded secret information and the associated requestors is eliminated.

Abstract: Disclosed herein is an apparatus which may comprise a plurality of nodes. In one example embodiment, each of the plurality of nodes may include one or more central processing units (CPUs), a random access memory device, and a parallel link input/output port. The random access memory device may include a local memory address space and a global memory address space. The local memory address space may be accessible to the one or more CPUs of the node that comprises the random access memory device. The global memory address space may be accessible to CPUs of all the nodes. The parallel link input/output port may be configured to send data frames to, and receive data frames from, the global memory address space comprised by the random access memory device(s) of the other nodes.

Abstract: Presented herein are systems, methods, and apparatus for encoding video data. In one implementation the method and system classify at least one macroblock of at least one original reference picture and select an encoding technique at least in part based on the classification of the at least one macroblock.

Abstract: Methods and systems for robust watermark insertion and extraction for digital set-top boxes are disclosed and may include descrambling, detecting watermarking messages in a received video signal utilizing a watermark message parser, and immediately watermarking the descrambled video signal utilizing an embedded CPU. The embedded CPU may utilize code that may be signed by an authorized key, encrypted externally to the chip, decrypted, and stored in memory in a region off-limits to other processors. The video signal may be watermarked in a decompressed domain. The enabling of the watermarking may be verified utilizing a watchdog timer. The descriptors corresponding to the watermarking may be stored in memory that may be inaccessible by the main CPU. The watermark may comprise unique identifier data specific to the chip and a time stamp, and may be encrypted utilizing an on-chip combinatorial function.

Abstract: An NFC-enabled device including tag emulation circuitry and reader emulation circuitry operates so as to provide a signal strength meter function. The signal strength meter function, in tag emulation mode, measures and reports on how well the tag is coupled to a third party reader field. In reader emulation mode, the signal strength meter function measures and reports how well the reader of the NFC-enabled device couples to a tag that is being read. One exemplary method includes detecting an NFC reader field, operating reader receiver circuitry at the NFC-enabled device so as to at least determine the strength of a signal received from the reader field, generating information representative of the determined strength of the signal received from the reader field at a first time, and performing one or more predetermined actions based at least in part on the one or more signals representative of the determined strength.

Abstract: There is presented a high bandwidth circuit for high-speed transceivers. The circuit may comprise an amplifier combining capacitor splitting, inductance tree structures, and various bandwidth extension techniques such as shunt peaking, series peaking, and T-coil peaking to support data rates of 45 Gbs/s and above while reducing data jitter. The inductance elements of the inductance tree structures may also comprise high impedance transmission lines, simplifying implementation. Additionally, the readily identifiable metal structures of inductors and t-coils, the equal partitioning of the load capacitors, and the symmetrical inductance tree structures may simplify transceiver implementation for, but not limited to, a clock data recovery circuit.

Abstract: The present invention includes a method of determining a phase estimate for an input signal having pilot symbols. The method includes receiving a plurality of pilot symbols, and then multiplying two or more pilot symbol slots by corresponding correlator coefficients to correct a phase estimate of the input signal.

Abstract: The disclosure is directed to a semiconductor wafer, integrated circuit product, and method of making same, having multiple non-singulated chips separated by scribe lines, comprising a plurality of seal rings, each seal ring surrounding a corresponding chip and disposed between the corresponding chip and adjacent scribe lines. Well resistors are disposed below the seal rings and probe pads disposed in the scribe lines. In particular, at least one of the probe pads is coupled by at least one of the well resistors to at least one of the chips.

Abstract: Methods and systems are disclosed herein to provide payment delegation for transactions. A payment request may be transmitted to a point of sale system from a mobile device. The mobile device owner may request that payment details for the transaction be obtained from a third-party device, such as a parent's computer. The point of sale system may transmit an approval request to the third-party device, or the mobile device may transmit an approval request to the third-party device. Upon receipt of payment details, the payment details may be communicated, and the transaction may be completed.

Abstract: A technique to use an auxiliary varactor coupled to a tuning varactor, in which a temperature compensated bias signal adjusts a bias on the auxiliary varactor to maintain a voltage controlled oscillator (VCO) from drifting in frequency as operating temperature for the VCO changes.

Abstract: Embodiments of a receiver for using a first oscillator signal provided by a crystal resonator to support multiple, different functionalities are provided. The receiver comprises a phase-locked loop (PLL) configured to provide a second oscillator signal based on the first oscillator signal provided by the crystal resonator; a first mixer configured to mix a received signal received over a first input path with the second oscillator signal received over a second input path to provide a first frequency-shifted signal; and an automatic frequency controller (AFC) configured to estimate a frequency offset of the second oscillator signal and adjust the PLL to compensate for the frequency offset. The receiver further can include solutions for mitigating potential sources of noise caused by the frequency of the first oscillator signal not being compensated for by the AFC.

Abstract: Provided is a low latency high bandwidth clock and data recovery (CDR) system. For example, there is a low latency high bandwidth CDR system including a demultiplexer configured to convert a high frequency input datastream to a low frequency output datastream according to a first latency and a phase error processor at least partially embedded into the demultiplexer and configured to determine a datastream phase error of the high frequency input datastream according to a second latency. The embedded phase error processor allows a portion of a total latency of the CDR system due to the demultiplexer and the phase error processor to be less than a sum of the first and second latencies.

Abstract: Aspects of a method and system for reducing transceiver power via a variable number of channels are provided. In this regard, utilization and/or availability of network and/or device resources may be determined and a configuration of channels utilized for transmitting data may be determined based on the determined utilization and/or availability of resources. Accordingly, the number of channels over which data is communicated may be altered based on determined thresholds for the utilization and/or availability of resources. Moreover, the configuration of channels utilized for communicating data may be dynamically altered by monitoring changes to the utilization and/or availability of resources. For example, the number of channels may be altered based on available bandwidth on one or more channels, based on capacity and/or available space of one or more buffers, and/or based on available power or desired power consumption of a transmitter.