Abstract: A vehicle communication network includes a network fabric, a plurality of vehicle control modules, memory, one or more multimedia processing modules, and a network manager. The network manager is operable to coordinate communication of packets, via the network fabric, among the vehicle control modules, the memory, and the multimedia processing modules based on individual content of the packets and in accordance with a global vehicle network communication protocol. The network manager is further operable to facilitate network resource management to support the communication of packets via the network fabric in accordance with the global vehicle network communication protocol.

Abstract: A network management module includes a network interface module, memory, and a processing module. The network interface module is operable for coupling the network management module to a vehicle communication network. The processing module is operable to manage a global vehicle network communication protocol that includes instituting a content-based network packet processing protocol and managing the vehicle communication network to support the network packet processing protocol. The content-based network packet processing protocol includes determining content type of a packet, determining a processing requirement of the packet, and prioritizing execution of the processing requirement based on the content type.

Abstract: A vehicle control module includes a vehicle device and a vehicle network interface. The vehicle device is operable to perform a vehicle function. The vehicle network interface facilitates communication regarding the vehicle function between the vehicle device and a vehicle network fabric in accordance with a global vehicle network communication protocol.

Abstract: Systems and methods to operate wireless devices are provided herein. In an exemplary system a first wireless device coupled to a consumer electronics device is operated in a sleep mode. It is determined whether there is a second device is operating in the same bandwidth spectrum as the first device. If there is a second device operating in the same bandwidth spectrum, then the first device is switched to a sniff mode of operation.

Abstract: A data bridge controls the transfer of packets between different priority network fabrics of a closed network, e.g. high and low priority network fabrics a vehicular network. Processing circuitry determines first priority routing of a first packet from the first network fabric to the second network fabric based on packet content type of the first packet and priority conditions of the second network fabric. A determination is also made regarding whether a second packet is to be delivered from the second network fabric to the first network fabric. If the second packet is to be delivered, second priority routing of the second packet is made based on packet content type of the second packet and priority conditions of the first network fabric.

Abstract: A data bridge controls packet transfers between network fabrics forming a closed network, such as a vehicular network. The data bridge includes two or more sets of modules, each of which communicates with a different network fabric. When a packet is to be delivered between network fabrics, a first set of modules, which is used to communicate with a first network fabric, decides whether to accept the packet or discard it. If the packet is accepted, it is delivered to a second set of modules, which is used for communicating with a second network fabric. The second set of modules makes a second, independent decision about whether the packet will be sent to the second network fabric. Each set of modules can base its decision on packet content type, and may discard any packet not to be delivered to the other network.

Abstract: Methods and systems for matching networks embedded in an integrated circuit package are disclosed and may include controlling impedance within an integrated circuit via one or more impedance matching networks. The impedance matching networks may be embedded within a multi-layer package bonded to the integrated circuit. The impedance of one or more devices within the integrated circuit may be configured utilizing the impedance matching networks. The multi-layer package may include one or more impedance matching networks. The impedance matching networks may provide impedance matching between devices internal to the integrated circuit and external devices. The impedance matching networks may be embedded within the multi-layer package, and may include transmission lines, inductors, capacitors, transformers and/or surface mount devices. The impedance matching networks may be deposited on top of and/or on bottom of the multi-layer package. The integrated circuit may be flip-chip bonded to the multi-layer package.

Abstract: A vehicle black box includes a memory device for receiving and storing real-time data associated with the vehicle during a recording time window. Upon determining that an accident has occurred, circuitry freezes the recording time window and stores the real-time data within the frozen recording time window within a one-time programmable (OTP) memory.

Abstract: A vehicular network is a closed network with known sources, destinations, and network connections that can be mapped in advance, and used to identify network resources needed to transmit a packet from a source to a destination. A network module can determine the source destination, and a priority of a packet based on the packet's content. Using the source and destination information, along with a network topology data, the network module can determine if two packets need the same network resources to be delivered to their destination. When the two packets do not use the same resources, there is no conflict, and the packets can be transmitted concurrently regardless of whether one of the packets has a higher priority than another packet. If there is a conflict, the network module transmits the packets based on the packets' priorities.

Abstract: Distributed processing LDPC (Low Density Parity Check) decoder. A means is presented herein that includes an LDPC decoding architecture leveraging a distributed processing technique (e.g., daisy chain) to increase data throughput and reduce memory storage requirements. Routing congestion and critical path latency are also improved thereby. Each daisy chain includes a number of registers, and a number of localized MUXs (e.g., MUXs having merely 2 inputs each). The means presented herein also does not contain any barrel shifters, high fan-in multiplexers, or interconnection networks; therefore, the critical path is relatively short and it can also be pipelined to further increase data throughput. If desired, a communication device can include multiple configurations of such daisy chains to accommodate the decoding of various LDPC coded signals (e.g., such as for an application and/or communication device that must decoded LDPC codes using different low density parity check matrices).

Abstract: A wireless device, for each of a plurality of wireless networks, establishes communications with each wireless network and transmits SIM card information to the wireless network. The plurality of wireless networks transmit SIM card authentication information requests to a cash card SIM server computer and, if a service agreement exists with an operator of the cash card SIM server, receives SIM card authentication challenge information. At least two of the wireless networks then authenticate the wireless device and prepare and transmit wireless service terms to the wireless device. The wireless device selects a servicing wireless network from the at least two wireless networks based upon the corresponding received wireless service terms and receives wireless service from the selected wireless network. The wireless network and cash card SIM server coordinate billing for such service and deduct appropriate amount(s) from the account of the SIM card.

Abstract: A wireless local area network (WLAN) transceiving integrated circuit includes a WLAN interface, an input buffer, an input buffer controller, and a processor. The WLAN transceiving integrated circuit may also include an output buffer, an output buffer controller, a transcoder, and/or an audio Coder-Decoder (CODEC). The WLAN transceiving integrated circuit is installed in a WLAN device that services voice communications. The input buffer receives packetized audio data from the WLAN interface. When the input buffer satisfies a buffer vacancy threshold, the processor and the input buffer controller cooperatively operate to fill at least a portion of the input buffer with packetized audio data. The processor copies packetized audio data from the input buffer and fills the input buffer with the copied packetized audio data to maintain an audio pattern in the input buffer. The input buffer controller fills the input buffer when the processor is available and after copying/filling is no longer effective.

Abstract: A programmable transmitter generates a frame preamble to train a receiver with respect to a communication link format that corresponds to a transmission mode wherein the transmission mode may comprise transmitting the communication link over one or more antennas. Generally, the invention includes generating a preamble with an arrangement that depends upon whether a Greenfield (high data rate) or mixed mode transmission is to occur and that depends upon a number of spatial streams that are to be generated. One format for high data rate transmission includes a short training sequence, a long training sequence and a signal field. The mixed mode transmission further includes a legacy prefix.

Abstract: Methods and systems for audio CODEC voice ADC processing are disclosed. Aspects of one method may include using a decimating filter that may be enabled to generate 13 MHz, 9-level digital output signal from a 26 MHz, 3-level digital input signal. The 13 MHz, 9-level digital output signal may be processed for RF transmission, for audio output to an output device, and/or utilized for testing by a test fixture, for example. The 13 MHz, 9-level digital output signal may be further processed to generate a 6.5 MHz, 33-level digital signal. The 6.5 MHz, 33-level digital signal may be converted to an analog signal, and processed for audio output and/or testing. The 13 MHz, 9-level digital output signal may also be processed to generate a 40 KHz, 17-bit digital signal, which may be communicated to a test equipment or further processed for RF transmission.

Abstract: Aspects of a method and system for frame timing acquisition in evolved universal terrestrial radio access (EUTRA) may include determining a received secondary synchronization sequence (SSS) based on a selected cyclic prefix length and on synchronization of a primary synchronization sequence (PSS). A first portion of information associated with the received SSS may be processed separately from a second portion of information associated with the received SSS. A frame timing and/or base station identifier may be determined by comparing the processed first portion of information with the processed second portion of information. The cyclic prefix length may be selected from a finite set of possible cyclic prefix lengths. The cyclic prefix length may be, for example, 9 samples or 32 samples. The primary synchronization sequence synchronization may be determined via correlation.

Abstract: A plurality of baseband clock signals by detecting an interference condition associated with at least one of the plurality of baseband clock signals and by spreading the spectrum of the at least one of the plurality of baseband clock signals when the interference condition is detected.

Abstract: A first plurality of characteristics are received from a first client device relating to transmissions received by the first client device from both an access point and a second client device. A second plurality of characteristics are received from the second client device relating to transmissions received by the second client device from both the access point and the first client device. The first plurality of characteristics and the second plurality of characteristics are both assessed. Based on the assessment, a least one of a plurality of customized power levels is selected for transmissions by the access point to the first client device and the second client device.

Abstract: In a method of automatically identifying a format of a video signal, where the video signal includes HSync pulses, VSync pulses, and video display data, the video signal is received, information about timing and width characteristics of the HSync pulses and the VSync pulses is extracted from the video signal, and the format of the video signal is determined based on the extracted information.

Abstract: A baseband digital processing module operates cooperatively with an analog signal processing module to effectuate highly adjustable and highly accurate gain adjustment in accordance with transmitter processing within a communication device. The gain adjustment and/or gain control is partitioned between the digital and analog domains by employing two cooperatively operating digital and analog modules, respectively. Gain adjustment in the analog domain is performed in a relatively more coarse fashion that in the digital domain. If desired, gain adjustment in each of the analog and digital domains is performed across a range of discrete steps. The discrete steps in the analog domain are larger than the discrete steps in the digital domain. Also, the discrete steps in the digital domain may be interposed between two successive discrete steps in the analog domain.

Abstract: A universal authentication token is configured to securely acquire security credentials from other authentication tokens and/or devices. In this manner, a single universal authentication token can store the authentication credentials required to access a variety of resources, services and applications for a user. The universal authentication token includes a user interface, memory for storing a plurality of authentication records for a user, and a secure processor. The secure processor provides the required cryptographic operations to encrypt, decrypt, and/or authenticate data that is sent or received by universal token. For example, secure processor may be used to generate authentication data from seed information stored in memory.