Abstract: A circuit and method utilizing a power control data bus for implementing power control. Various aspects of the present invention provide an electrical circuit that comprises a power supply circuit that outputs electrical power. The electrical circuit may also comprise an integrated circuit that receives electrical power from the power supply circuit. The electrical circuit may also comprise a power control data bus, which communicatively couples a power control data bus interface of the power supply circuit and a power control data bus interface of the integrated circuit. The power control data bus may, for example, carry power control data between the integrated circuit and the power supply circuit. Various aspects of the present invention also provide a method that comprises communicating power control data over a power control data bus and utilizing the power control data to control characteristics of electrical power provided to an integrated circuit or module.

Abstract: A method and apparatus is disclosed to compensate for interference and/or distortion impressed onto a transmitted communication signal in the presence of one or more time-varying noise and/or interference conditions. A communications receiver includes a noise analyzer to characterize the composition of the interference and/or the distortion impressed onto a transmitted communication signal in the presence of one or more time-varying noise and/or interference conditions. In an exemplary embodiment, the communications receiver selects at least one set of equalization coefficients and/or updates at least one parameter of a least-squares algorithm or the suitable equivalent algorithm to compensate for a particular interference and/or the distortion impressed onto the transmitted communication signal.

Abstract: Methods and systems for a low noise amplifier with tolerance to large inputs are disclosed and may include generating at least one control signal that controls a plurality of directional modes of at least one contact pad on a mobile multimedia processor (MMP) in an integrated circuit. Selectable modes may include: bidirectional, input, and an output mode. Each of the modes includes a bypass mode and a processing mode that may be controlled by the generated control signal. Received data may be processed by circuitry in the MMP when the processing mode may be enabled. Received data may be passed through the MMP without being processed by the MMP when the bypass mode may be enabled. An additional signal may be generated to dynamically pull-down a potential of the at least one contact pad and/or to pull-up a potential of said at least one contact pad.

Abstract: A startup protocol is provided for use in a communications system having a plurality of transceivers, one transceiver acting as a master and another transceiver acting as slave, each transceiver having a noise reduction system, a timing recovery system and at least one equalizer. The operation of the startup protocol is partitioned into three stages. During the first stage the timing recovery system and the equalizer of the slave are trained and the noise reduction system of the master is trained. During the second stage the timing recovery system of the master is trained in both frequency and phase, the equalizer of the master is trained and the noise reduction system of the slave is trained. During the third stage the noise reduction system of the master is retrained, the timing recovery system of the master is retrained in phase and the timing recovery system of the slave is retrained in both frequency and phase.

Abstract: In an embodiment, an apparatus and method reduces a calibration settling time in an analog-to-digital converter (ADC). The ADC has a reference voltage supply. The reference voltage supply has an output. A filter capacitor is coupled to the reference voltage supply output. An isolation transistor is series-coupled between the filter capacitor and ground. The isolation transistor isolates the filter capacitor during calibration of the ADC.

Abstract: Certain embodiments of the invention may be found in a method and system for performing SCSI read operations with a CRC via a TCP offload engine. Aspects of the method may comprise receiving an iSCSI read command from an initiator. Data may be fetched from a buffer based on the received iSCSI read command. The fetched data may be zero copied from the buffer to the initiator and a TCP sequence may be retransmitted to the initiator. A digest value may be calculated, which may be communicated to the initiator. An accumulated digest value stored in a temporary buffer may be utilized to calculate a final digest value, if the buffer is posted. The retransmitted TCP sequence may be processed and the fetched data may be zero copied into an iSCSI buffer, if the buffer is posted. The calculated final digest value may be communicated to the initiator.

Abstract: A system and method that support display of video fields using related data encoded in data structures. Each data structure is associated with one video field and contains all the information associated with the display of the video field. The data structure is encoded with the video field that is displayed exactly one field prior to the field associated with the data structure. In an embodiment of the present invention, the data structure contains all the information associated with the display of a video field, regardless of whether certain data changes from one field to the next.

Abstract: A system for handling calls using simulcasting of multimedia information via a gateway device communicatively coupled to a wide area network, the system including at least one processor for use in an access device, the at least one processor arranged to communicate to the wide area network using at least one wireless interface of the access device, the at least one processor operable to, at least associate the access device with the gateway device; communicate multimedia and call information with the wideband network using the at least one wireless interface; send, to the gateway device via the wide area network, a request to record the call information communicated during a call over the wide area network; and receive, from the gateway device via the broadband network, acceptance of the request to record the call information, if resources needed for recording the call information communicated during the call are available.

Abstract: A device includes a processing module, a millimeter wave (MMW) oscillation module, a MMW beamforming module, and a plurality of amplifiers. The processing module determines activation of the device and thereafter modulates data to produce modulated data, determines a beamforming setting, and establishes a transmit power setting. The MMW oscillation module generates a modulated MMW signal based on the modulated data. The MMW beamforming module converts the modulated MMW signal into a plurality of MMW beamformed signals based on the beamforming setting. The plurality of amplifiers amplifies the plurality of MMW beamformed signals in accordance with the transmit power setting to produce a MMW near field transmission.

Abstract: Local oscillation circuitry for use in an RF transceiver Integrated Circuit (IC) includes local oscillation generation circuitry operable to produce a local oscillation and local oscillation distribution circuitry. The local oscillation distribution circuitry includes a splitting circuit, a first distribution portion, and a second distribution portion. The splitting circuit receives the local oscillation and produces multiple copies of the local oscillation. The first distribution portion produces a first local oscillation corresponding to a first RF band and a second local oscillation corresponding to a second RF band based and to provide the first local oscillation and the second local oscillation to a first RF transceiver group. The second distribution portion produces a first local oscillation and a second local oscillation and provides the first local oscillation and the second local oscillation to the second RF transceiver group.

Abstract: An integrated radar system includes a processing module and a radar device. The radar device includes an antenna module, a configurable shaping module, and a configurable transceiver module. The processing module generates an outbound signal and a control signal to configure the integrated radar system. The configured transceiver module converts the outbound signal into an outbound wireless signal. The configured shaping module shapes the outbound wireless signal into a shaped signal. The antenna module transmits the shaped signal and then receives an inbound radar signal. The configured shaping module shapes the inbound radar signal into an inbound wireless signal. The configured transceiver module converts the inbound wireless signal into an inbound symbol stream. The processing module determines location information regarding an object based on the inbound symbol stream.

Abstract: According to one disclosed embodiment, an on-chip resistor calibration circuit includes an RC oscillator having a test resistor and a precision capacitor as elements, a counter, and a reference clock. In one embodiment, an RC oscillator generates a waveform having a period dependent upon the resistance of the test resistor and the capacitance of the precision capacitor. In such an embodiment, a counter and a reference clock may be configured to measure the period of the waveform. Using a pre-determined capacitance of the precision capacitor, a resistance of the test resistor may be determined. In another embodiment, an RC oscillator generates first and second waveforms through use of an additional capacitor that can be switched in and out of the RC oscillator circuit. Using a pre-determined capacitance of the precision capacitor, an RC product of the test resistor and the additional capacitor may be determined.

Abstract: Methods, systems, and apparatuses are provided for three-dimensional coiling via structures. A substrate includes a plurality of insulating layers, a plurality of trace layers interleaved with the insulating layers, and a three-dimensional coiling via. The three-dimensional coiling via includes a plurality of electrically conductive traces and a plurality of electrically conductive vias through the insulating layers. The electrically conductive traces are present in at least two of the traces layers and are coupled together by the electrically conductive vias. The electrically conductive traces are arranged to form at least one partial turn around an axis through the substrate.

Abstract: Techniques are described herein that suppress noise in a Mel-filtered spectral domain. For example, a window may be applied to a representation of a speech signal in a time domain. The windowed representation in the time domain may be converted to a subsequent representation of the speech signal in the Mel-filtered spectral domain. A noise suppression operation may be performed with respect to the subsequent representation to provide noise-suppressed Mel coefficients.

Abstract: A beamforming radio frequency (RF) circuit includes a plurality of antennas, a plurality of amplifiers and an adjust module. The plurality of antennas is operably coupled to interrelate a plurality of beamformed signal components with a beamformed signal. The plurality of amplifiers is operably coupled to interrelate the plurality of beamformed signal components with a plurality of adjusted signal components. The adjust module is operably coupled to interrelate coordinates of a signal with the plurality of adjusted signal components.

Abstract: Aspects of the invention may be found in a method and system for testing an integrated circuit and may comprise an address selector, data selector and staging register coupled to a signal generator. The address selector may comprise a direct access memory test (DAMT) mode address control input and one or more output address pins coupled to an embedded memory device under test (DUT). The data selector may be coupled to at least one data pin and control pin of the signal generator and may comprise a DAMT mode data control input and at least one data output coupled to embedded memory DUT. A staging register comprising a first output clock rate which is one-quarter (¼) its input clock rate and matches a DUT burst write frequency may be coupled to an input of the data selector. A DAMT mode control may configure the memory DUT for DAMT operation.

Abstract: According to one exemplary embodiment, a method and system for determining and removing DC offset in an AC signal includes receiving an AC signal having a first-channel and a second-channel, e.g. an I-channel and a Q-channel, receiving a plurality of first-channel and second-channel samples, storing a negative first-channel sample corresponding to a first sign change in the plurality of second-channel samples, and storing a positive first-channel sample corresponding to a second sign change in the plurality of second-channel samples. The method further includes determining an average value of the negative first-channel sample and the positive first-channel sample, where the average value is the DC offset in the first-channel. The method can further include subtracting the determined DC offset from samples received in the first-channel (or the second-channel) prior to demodulation. The method and system can be implemented in, for example, a Bluetooth receiver.

Abstract: A wireless transceiver includes a phased array of antennas, that transmit an outbound RF signal containing outbound data to remote transceivers and that receives an inbound RF signal containing inbound data from the remote RF transceivers, wherein the phased array of antennas is configurable based on a control signal. An antenna configuration controller generates the control signal to configure the phased array of antennas to hop among a plurality of radiation patterns based on a hopping sequence. An RF transceiver section generates the outbound RF signal based on the outbound data and that generates the inbound data based on the inbound RF signal. In one configuration, a switching section selectively couples a selected antenna of the phased array of antennas to the RF transceiver section, based on the control signal. In another configuration, the RF transceiver section includes an RF section for each antenna of the phased array of antennas.

Abstract: A firmware data processing system may be operable to allocate a configuration area in the firmware binary image file for customizable settings. During the firmware build process for the firmware binary image file, default configuration information may be inserted into this configuration area. This default configuration information may be either actual default setting values or indicator to use the default setting values. During post-build modification process, a separately created utility application may be operable to read in the original firmware binary image file, select new settings, and insert new configuration information into the configuration area. The utility application may also be operable to create a new firmware binary image file with reproduced checksums or other error detection mechanisms required for the original firmware binary image file, based on the new configuration information in the configuration area.

Abstract: Method of processing a transmitted encoded media data stream is received. If a data element arrives prior to, or at, a predetermined playout deadline, the data element is decoded, the media represented by the decoded data element is played, and the data element is provided to a decoder state machine to update a decoder state. If a data element arrives after the predetermined playout deadline, the data element is provided to the decoder state machine to update the decoder state. In one embodiment, if the specified data element fails to arrive by the playout deadline, a subsequently received data element is saved in memory. Then, if the specified data element arrives after the predetermined playout deadline, the specified data element and the saved, subsequently received, data element are provided to the decoder state machine to update the decoder state.