Abstract: A multi-speed burst mode serializer/de-serializer (SerDes) is configurable and can operate in one of a plurality of operating modes. The plurality of operating modes correspond to the reception of signals from optical network units that operate at different nominal speeds. These various modes of operation can enable a single SerDes design to apply to a variety of speeds and network configurations (e.g., point-to-point or point-to-multipoint). In one example, the design can be initially configured for operation with a single ONT or a network of ONTs at a single speed, or can be dynamically configured during operation for use with a network of ONTs operating at different speeds.

Abstract: Described herein is a rate controller in a video system. The rate controller is comprised of a complexity estimator, a quantization level selector, a complexity generator, and a complexity estimate updater. The complexity estimator generates a complexity metric estimate. The quantization level selector sets a quantization level based on the complexity metric estimate. The complexity generator generates an actual complexity metric. The complexity estimate updater generates an updated complexity metric estimate based on a difference between the complexity metric estimate and the actual complexity metric.

Abstract: A dual purpose serializer/de-serializer (SerDes) for point-to-point and point-to-multipoint communication. A configurable SerDes can be designed to operate in one of a plurality of operating modes. Selection between the plurality of operating modes can be based on information received via a management interface. In one example, the various operating modes can be defined with different locking times and jitter characteristics.

Abstract: Frame processing for a wireless communication system. The frame processing includes detecting reception of a frame based on a portion of a preamble of a frame, wherein the frame includes a preamble and a data payload. With detecting the reception of a frame, determining a frame type of a plurality of frame types from at least the portion of the preamble. Processing a remaining portion of the preamble in accordance with the frame type to determine payload processing parameters, and processing the data payload based on the payload processing parameters.

Abstract: A network device for cancelling spurs without affecting an incoming signal. The network device includes an estimator for estimating amplitude and phase of a spur over a predetermined period of time. The network device also includes processing means for freezing further estimation of the amplitude and phase of the spur, for cancelling for an estimated spur and for allowing incoming packets. The network device further includes subtracting means for subtracting the estimated spur from an incoming packet. The estimated spur is subtracted from the incoming packet without affecting incoming signals that are not part of the estimated spur.

Abstract: Aspects for secure access and communication of information in a distributed media network may include detecting when a legacy media peripheral is connected to a PC and/or a media processing system on the distributed media network. One or more identifiers associated with the legacy media peripheral may be established and utilized to facilitate communication of the legacy media peripheral over the distributed media network. At least one legacy media peripheral identifier and at least one identifier of a user utilizing the legacy media peripheral may be requested. The legacy media peripheral identifier may be a serial number of the legacy media peripheral, while the user identifier may be a user password and/or a user name. Media peripheral association software may be executed on the PC and/or the media processing system and utilized for media peripheral association and authentication in accordance with various embodiments of the invention.

Abstract: A system and method for storing power utilization information in an integrated circuit and utilizing such information. Various aspects of the present invention provide an integrated circuit that comprises a first module, which stores power utilization information for at least a portion of the integrated circuit. A second module of the integrated circuit may communicate the power utilization information with an electrical device external to the integrated circuit. Various aspects of the present invention provide a method for storing power utilization information in an integrated circuit. For example, a performance characteristic and/or a power supply characteristic may be monitored as the integrated circuit is utilized. Power utilization information may be determined from the monitored characteristic(s), and the power utilization information may be stored in the integrated circuit.

Abstract: Systems and methods for providing SRV node selection are provided. The method may include using a node in a home communications network. The communications network may include a plurality of nodes and a coaxial cable. The method may include using an entry node to submit a query message in selected fields of a Device Attribute Information Element in L2ME protocol. The entry node may require an advanced service. The entry node may not be aware which node of the plurality of nodes is the node selected for supporting the advanced service on the network. The selected fields may include vendor specific fields. The method may further include distributing the query message to the plurality of nodes. In response to the query message, the method may further include determining which of the plurality of nodes can be selected for supporting the advanced service on the network.

Abstract: Various example embodiments are disclosed. According to an example embodiment, a method may include determining, by a port processor, a buffer length based on an amount of data stored in a port controlled by the port processor, comparing the buffer length to a low-power buffer threshold, determining a link utilization based on a number of packets transmitted by the port, comparing the link utilization to a link utilization threshold, and placing the port into a low-power state based on the comparison of the buffer length to the low-power buffer threshold and the comparison of the link utilization to the link utilization threshold.

Abstract: According to an exemplary embodiment, an interposer structure for electrically coupling a semiconductor die to a support substrate in a semiconductor package includes at least one through-wafer via extending through a semiconductor substrate, where the at least one through-wafer via provides an electrical connection between the semiconductor die and the support substrate. The interposer structure further includes a passive component including a trench conductor, where the trench conductor extends through the semiconductor substrate. The passive component further includes a dielectric liner situated between the trench conductor and the semiconductor substrate. The passive component can further include at least one conductive pad for electrically coupling the trench conductor to the semiconductor die. The passive component can be, for example, an inductor or an antenna.

Abstract: An integrated circuit can include an I/O pad, an internal circuit, an inductor, an electrostatic discharge (ESD) protection circuit, and an ESD clamp. The internal circuit can be biased with a first voltage supply and a second voltage supply, where the internal circuit is connected to the I/O pad at a first node. The ESD protection circuit can be connected between the first node and a second node. The inductor can be connected between the second node and a third voltage supply. Further, the ESD clamp can be connected between the second node and the second voltage supply.

Abstract: Aspects of a method and system for transmission or reception of FM signals utilizing a DDFS clocked by an RFID PLL are provided. In this regard, one or more signals utilized to transmit or receive FM communication may be generated by clocking a DDFS via a signal generated to enable RFID communication. The DDFS may be controlled via a control word from a processor. In this regard, the control word may determine a frequency and/or phase of the signals output by the DDFS. The control word may be switched between two or more values to generate different frequencies and/or phases in different time intervals. Additionally, the control word may be adjusted to maintain a constant phase and/or frequency in spite of changes to the signal clocking the DDFS.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic with inductive broadbanding fabricated in conventional CMOS process technology. Optimum balance between power consumption and speed for each circuit application is achieved by combining high speed C3MOS logic with inductive broadbanding/C3MOS logic with low power conventional CMOS logic. The combined C3MOS logic with inductive broadbanding/C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: Certain aspects of a method and system for supporting hardware acceleration for iSCSI read and write operations via a TCP offload engine may comprise pre-registering at least one buffer with hardware. An iSCSI command may be received from an initiator. An initiator test tag value, a data sequence value and/or a buffer offset value of an iSCSI buffer may be compared with the pre-registered buffer. Data may be fetched from the pre-registered buffer based on comparing the initiator test tag value, the data sequence value and/or the buffer offset value of the iSCSI buffer with the pre-registered buffer. The fetched data may be zero copied from the pre-registered buffer to the initiator.

Abstract: A method and device for transmitting a frame of a wireless communication begins by generating a preamble of the frame that includes a short training sequence and at least one long training sequence. The at least one long training sequence includes non-zero energy on each of a plurality of subcarriers except a DC subcarrier. The at least one long training sequence corresponds to the number of antennas and applicable wireless communication standards. A matrix is defined to represent the at least one long training sequence. The preamble is compatible with legacy and current standards. A channel is defined with a set of sub carriers to transmit the frame.

Abstract: A real-time/non-real-time/RF IC includes first and second baseband processing modules, an RF section, a wireline interface, and a bus structure. The first baseband processing module converts real-time outbound data into real-time outbound symbols and converts real-time inbound symbols into real-time inbound data. The second baseband processing module converts non-real-time outbound data into non-real-time outbound symbols and converts non-real-time inbound symbols into non-real-time inbound data. The RF section converts the real-time outbound symbols into real-time outbound RF signals, converts real-time inbound RF signals into the real-time inbound symbols, converts the non-real-time outbound symbols into non-real-time outbound RF signals, and converts non-real-time inbound RF signals into the non-real-time symbols. The wireline interface couples the non-real-time outbound data, the non-real-time inbound data, the real-time outbound data, and/or the real-time inbound data to an off-chip wireline connection.

Abstract: A system and method for sharing a view between systems in a dynamic wireless communication network. Various aspects of the present invention may comprise a first system communicating information of a view to a display resource of the first system. The first system may establish a two-way wireless communication link between the first system and a second system in the dynamic wireless communication network. The second system may, for example, communicate a request to the first system for the first system to share a view with the second system. The first system may, for example, receive such a request and respond to such a request by communicating information of a view to the second system. The second system may then communicate information of the view to a display resource of the second system. Various aspects may comprise the first and second systems communicating view modification information between the systems.

Abstract: Presented herein are system(s), method(s), and apparatus for rapid switching between streams of data. In one embodiment, there is described a circuit for providing media. The circuit comprises a multiplexed stream processor, a queue, and a decoder. The multiplexed stream processor receives a multiplexed stream and filtering at least one elementary stream. The queue queues the at least one elementary stream. The decoder decodes the at least one elementary stream. The multiplexed stream processor filters at least another elementary stream instead of at least one elementary stream after issuance of a command to switch from the at least one elementary stream to the at least another elementary stream. The queue stores a portion of the at least one elementary stream after issuance of the command, said portion of the at least one elementary stream being written into the queue before issuance of the command.

Abstract: Aspects of a method and system for low power IDLE signal transmission in Ethernet networks are provided. In this regard, during time periods between transmissions of actual data by a local Ethernet link partner, the local Ethernet Link partner may generate one or more signals, in place of a standard Ethernet IDLE signal, that enable synchronization between Ethernet link partners. In this manner, the generated signals may enable reducing power consumption as compared to standard Ethernet IDLE signals. Accordingly, link activity may be monitored to enable detecting periods when there may be no actual data for transmission and the generated signals may be transmitted. The generated signals may be transmitted at a reduced symbol rate as compared to standard Ethernet IDLE signals. The generated signals may be transmitted via fewer network links as compared to standard Ethernet IDLE signals.

Abstract: A scheme for sharing antenna control pins in a wireless communications device implemented on a single CMOS integrated circuit is described. By providing a routing circuit for coupling the antenna control signal to the appropriate transceiver circuitry in a multi-transceiver system, antenna control signals may be efficiently processed using a minimum of pins on the wireless communication device.