Abstract: All digital RF modulator. An RF modulator, implemented using only digital techniques, obviates the need for an additional board, implemented using discrete analog components, to perform the necessary modulation to provide the RF output signal for use with a display device (television). Modern displays typically include functionality to support a number of input types beyond an RF input. However, older, legacy displays typically only support inputs that are RF in nature. A fully integrated solution that performs the RF modulation of the output signal that may be used in such legacy types systems is provided using digital techniques.

Abstract: A method having enhanced decoding operations associated with receiving multiple Radio Frequency (RF) Burst(s) is provided. Multiple RF burst(s) are received where the multiple RF Burst(s) include first RF bursts and second RF Burst(s). The second RF bursts may be transmitted in parallel or in response to a decoding error associated with the first RF burst. The received RF burst(s) are equalized and deinterleaved to yield extracted soft samples. Then the first estimated bit sequences and second estimated bit sequences are decoded from the extracted soft samples. A set of possible bit sequences may then be pruned based on based on combined knowledge of the first estimated bit sequence and the second estimated bit sequences. This pruned set may be compared using a sequence detector and the combined first estimated bit sequences and second estimated bit sequences to select a decoded bit sequence.

Abstract: A method for synchronizing receivers that receive turbo encoded signals to a received signal. Turbo encoding may enable signals to be decoded at a much lower signal to noise ratio than previously practical. A traditional method of synchronizing a receiver to an incoming signal is to use a slicer to determine a received symbol and then to compare the determined symbol to the incoming waveform, in order to adjust the phase of the slicer with respect to the incoming signal. At signal low levels, at which turbo encoded signals may be decoded, this slicing method may be prone to errors that may disrupt the synchronization of the receiver to the incoming signal. By replacing the slicer by a Viterbi decoder with zero traceback (i.e., one which does not consider future values of the signal only past values) a prediction as to what the incoming signal is can be made.

Abstract: An integrated communications system. Comprising a substrate having a receiver disposed on the substrate for converting a received signal to an IF signal. Coupled to a VGA for low voltage applications and coupled to the receiver for processing the IF signal. The VGA includes a bank pair having a first bank of differential pairs of transistors and a second bank of differential pairs of transistors. The bank pair is cross-coupled in parallel, the IF signal is applied to the bank pair decoupled from a control signal used to control transconductance output gain of the bank pair over a range of input voltages. A digital IF demodulator is disposed on the substrate and coupled to the VGA for low voltage applications, for converting the IF signal to a demodulated baseband signal. And a transmitter is disposed on the substrate operating in cooperation with the receiver to establish a two way communications path.

Abstract: A system and method that provide full color mapping of video images with minimal distortion to the image. A two-dimensional look up table may be used to map a certain number of colors, and for colors that are not represented by entries in the table, the four closest entries to the desired color may be interpolated to provide mapping for the color, thus achieving full color mapping. The method may also provide the ability to map colors in partial bypass and full bypass conditions. In a full bypass condition the color goes through the system unchanged, and the system may be capable of mapping the brightness of the color by interpolating the luminance values of the closest table entries.

Abstract: LDPC (Low Density Parity Check) coded modulation symbol decoding. Symbol decoding is supported by appropriately modifying an LDPC tripartite graph to eliminate the bit nodes thereby generating an LDPC bipartite graph (such that symbol nodes are appropriately mapped directly to check nodes thereby obviating the bit nodes). The edges that communicatively couple the symbol nodes to the check nodes are labeled appropriately to support symbol decoding of the LDPC coded modulation signal. The iterative decoding processing may involve updating the check nodes as well as estimating the symbol sequence and updating the symbol nodes. In some embodiments, an alternative hybrid decoding approach may be performed such that a combination of bit level and symbol level decoding is performed. This LDPC symbol decoding out-performs bit decoding only. In addition, it provides comparable or better performance of bit decoding involving iterative updating of the associated metrics.

Abstract: A packet-based, hierarchical communication system, arranged in a spanning tree configuration, is described in which wired and wireless communication networks exhibiting substantially different characteristics are employed in an overall scheme to link portable or mobile computing devices. The network accommodates real time voice transmission both through dedicated, scheduled bandwidth and through a packet-based routing within the confines and constraints of a data network. Conversion and call processing circuitry is also disclosed which enables access devices and personal computers to adapt voice information between analog voice stream and digital voice packet formats as proves necessary. Routing pathways include wireless spanning tree networks, wide area networks, telephone switching networks, internet, etc., in a manner virtually transparent to the user.

Abstract: A cable modem system and method is provided for supporting data transfer protocols that extend beyond standard protocols used in conventional data over cable systems. A cable modem in accordance with the invention determines, during registration, whether a CMTS with which it communicates is capable of supporting an extended protocol, and if it is, transfers data to the CMTS in accordance with the extended protocol. Additionally, a CMTS in accordance with the invention is notified during registration whether or not a cable modem supports an extended protocol and stores this information. When a request for transmission opportunity is subsequently received from the cable modem, the CMTS accesses the stored information to determine if the cable modem supports the extended protocol. If the cable modem supports the extended protocol, the CMTS processes data received from the cable modem during the transmission opportunity in accordance with that protocol.

Abstract: A phase locked loop (PLL) a phase detector, a charge pump, a loop filter, a controlled oscillator, and a feedback divider. The phase detector is coupled to produce a difference signal based on a difference between phase of a reference oscillation and phase of a feedback oscillation. The charge pump is coupled to convert the difference signal into an up-signal or a down signal. The loop filter coupled to filter the up signal or the down signal to produce a control signal. The controlled oscillator is coupled to generate an output oscillation based on the control signal. The feedback divider is coupled to generate the feedback oscillation from the output oscillation based on a divider value. The loop filter includes a first resistor-capacitor circuit and a second resistor-capacitor circuit. The first resistor-capacitor circuit is calibrated using a first calibration technique and the second resistor-capacitor circuit is calibrated using a second calibration technique.

Abstract: According to the present invention, the bandwidth of a TDD channel is increased where multiple slave devices communicate with a master device over the channel. According to an aspect of the present invention, the master device can increase channel bandwidth by utilizing available transmit slots that occur during receipt of a multi-slot packet from a slave device. For example, the master device receives a first packet at a first frequency from a first slave via the channel. The master determines whether the first packet is a multi-slot packet, and if so, transmits a second packet to a second slave via the channel at a second frequency different from the first frequency. The second packet is transmitted after receipt of the first packet, but prior to the end of the first packet.

Abstract: A (radio frequency) RF transmission system includes an RF transmitter that generates an RF signal at a sequence of selected carrier frequencies. A frequency hop module, coupled to the RF transmitter generates the sequence of selected carrier frequencies. A programmable antenna is tuned to each of the sequence of selected carrier frequencies to transmit the RF signal via an antenna current.

Abstract: A method and system for parameter generating for digital noise reduction based on bitstream properties is provided, which may comprise receiving at a host processor, a plurality of picture level parameters generated by a video decoder for a video stream. The host processor may control a digital noise reduction (DNR) module that processes input video from a video bus using the received plurality of picture level parameters.

Abstract: A video and graphics system processes video data including both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The video and graphics system includes a video decoder, which is capable of concurrently decoding multiple SLICEs of MPEG-2 video data. The video decoder includes multiple row decoding engines for decoding the MPEG-2 video data. Each row decoding engine concurrently decodes two or more rows of the MPEG-2 video data. The row decoding engines have a pipelined architecture for concurrently decoding multiple rows of MPEG-2 video data. The video decoder may be integrated on an integrated circuit chip with other video and graphics system components such as transport processors for receiving one or more compressed data streams and for extracting video data, and a video compositor for blending processed video data with graphics.

Abstract: A radio circuit includes a mixing module, a first adjustable resonant circuit and a second adjustable resonant circuit. The mixing module is coupled to mix a first signal having a first carrier frequency with a second signal having a second carrier frequency to produce a mixed signal having a frequency sum component and a frequency difference component. The first adjustable resonant circuit is tuned to resonant at a frequency corresponding to one of the frequency sum component and the frequency difference component. The second adjustable resonant circuit is tuned to resonant at a frequency corresponding to another one of the frequency sum component and the frequency difference component, wherein the first and second adjustable resonant circuits alter the mixed signal to produce a converted signal.

Abstract: Presented herein are systems and methods for efficiently storing macroblocks in DRAM. The macroblocks are stored contiguously allowing each macroblock to be written and overwritten in a single write transaction. Additionally, in one embodiment, as many as five macroblocks can be written or overwritten in a single write transaction.

Abstract: Joint decoding of ISI (Inter-Symbol Interference) channel and modulation codes. A single, combined ISI and modulation decoding module is operable to process a signal received from an ISI communication channel and directly to generate a soft estimate of information encoded therein. A single module employs a decoding transfer function that is substantially matched to the communication channel that introduces the ISI and the modulation encoding performed on the information before being launched into the ISI communication channel. Such operations and functionality are adaptable to a variety of modulation coding systems that are tailored to deal with communication systems that introduce ISI. Moreover, such operations and functionality are extendable to communication systems employing an error correction code (ECC) such as Reed-Solomon (RS) coding as well as ECCs of an iterative nature such as LDPC (Low Density Parity Check) coding, turbo coding, and/or turbo trellis code modulation (TTCM) coding.

Abstract: Direct detection of wireless interferers in a communication device for multiple modulation types. One or more radios implemented within a communication device is/are operative to receive and process wireless communications. A wireless communication signal is processed to extract symbols there from. Various symbols groups are processed in accordance with correlation processing to identify potential interferers (e.g., other communication devices using common portions of frequency spectra). Alternatively, matched filter processing (e.g., using a Barker matched filter in some embodiments) operates on the various symbol groups to identify some potential interferers. Various combinations of correlation processing and matched filter processing may be employed in other instances (e.g., using any of a desired means of comparison, combining, etc.) in considering interferers identified in accordance with each of these two means.

Abstract: A method and apparatus are provided for an embedded wireless interface that is embedded in, for example, one of an input and output controller device for controlling input and output communications with off-board devices, within a memory controller device and a processor motherboard. The embedded wireless interface may be utilized as a wireless test access point to provide signal stimulations for test purposes or to monitor communications over a specified wired communication link.

Abstract: Provided is a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).

Abstract: Hybrid location determination for wireless communication device. Various services that may be used by a wireless communication device within a particular location may be referred to as location based services (LBS). As such, means by which the location of a wireless communication device that may use such available services, within such a locale, is made by using more than one type of location determination approach. For example, a wireless communication device includes communication capability (e.g., RX and TX) in accordance with a first communication protocol (e.g., Bluetooth) and also includes a communication capability (e.g., RX only) in accordance with a second communication protocol (e.g., WiFi/WLAN (Wireless Local Area Network)). The RX capability is operative to assist in location determination for the wireless communication device based on knowledge of at least one wireless communication device that communicates with the wireless communication device.