Abstract: Methods, systems, and apparatuses for wafer-level package-on-package structures are provided herein. A wafer-level integrated circuit package that includes at least one die is formed. The wafer-level integrated circuit package includes redistribution interconnects that redistribute terminals of the die over an area that is larger than an active-surface of the die. Electrically conductive paths are formed from the redistribution interconnects at a first surface of the wafer-level integrated circuit package to electrically conductive features at a second surface of the wafer-level integrated circuit package. A second integrated circuit package may be mounted to the second surface of the wafer-level integrated circuit package to form a package-on-package structure. Electrical mounting members of the second package may be coupled to the electrically conductive features at the second surface of the wafer-level integrated circuit package to provide electrical connectivity between the packages.

Abstract: A wireless device includes impedance determination and processing circuitry. The impedance determination circuitry determines load impedance at an output of at least one Radio Frequency (RF) power amplifier of the wireless device. The processing circuitry couples to the impedance determination circuitry and alters at least one operating parameter of the wireless device based upon the determined load impedance.

Abstract: According to one general aspect, a method may include receiving data from a network device. In some embodiments, the method may include writing the data to a memory bank that is part of a plurality of at least single-ported memory banks that have been grouped to act as a single at least dual-ported aggregated memory element. In various embodiments, the method may include monitoring the usage of the plurality of memory banks. In one embodiment, the method may include, based upon a predefined set of criteria, placing a memory bank that meets the predefined criteria in a low-power mode.

Abstract: According to one embodiment, a method for selective gate halo implantation includes forming at least one gate having a first orientation and at least one gate having a second orientation over a substrate. The method further includes performing a halo implant over the substrate. The first orientation allows a halo implanted area to be formed under the at least one gate having the first orientation and the second orientation prevents a halo implanted area from forming under the at least one gate having the second orientation. The halo implant is performed without forming a mask over the at least one gate having the first orientation or the at least one gate having the second orientation. The at least one gate having the first orientation can be used in a low voltage region of a substrate, while the at least one gate having the second orientation can be used in a high voltage region.

Abstract: An integrated circuit (IC) device is provided. The IC device includes a first die having a surface with a first pad formed thereon, a second die having a surface with a second pad formed thereon, and a substrate interposer that couples the first pad to the second pad. The substrate interposer is coupled to the surface of the first die and the surface of the second die.

Abstract: The performance of an AGC loop typically depends on several factors, including gain linearity of the VGA and variation in the VGA bandwidth over the range of available gain settings. Although a resistively degenerated VGA provides for excellent gain linearity and immunity to process variations, the conventional architecture for a resistively degenerated VGA suffers from bandwidth variation over the range of available gain settings. Embodiments are provided herein of a constant-bandwidth VGA that utilizes resistive degeneration. To maintain a constant bandwidth over the range of available gain settings, degeneration resistors are coupled in parallel with compensation capacitors. In an embodiment, a compensation capacitor is determined to have a capacitance substantially equal to the decrease in total degeneration resistance that occurs as a result of an associated degeneration resistor being placed in parallel with the total degeneration resistance.

Abstract: According to one general aspect, an apparatus may include an ingress port, a header cache, and a plurality of ingress recursion engines. In some embodiments, the ingress port may be configured to receive a packet that comprises a data portion and a header portion, wherein the header portion comprises at least one header. In various embodiments, the header cache may be configured to store at least a part of the header portion of the packet. In one embodiment, the plurality of ingress recursion engines may be configured to recursively process the header portion, from outer-most header to inner-most header, until an adjacency value for the packet is determined. In some embodiments, each ingress recursion engine may be configured to process a header from the header portion.

Abstract: Embodiments of a SAW-less RF receiver front-end that includes a frequency translated notch filter (FTNF) are presented. An FTNF includes a passive mixer and a baseband impedance. The baseband impedance includes capacitors that form a low-Q band-stop filter. The passive mixer is configured to translate the baseband impedance to a higher frequency. The translated baseband impedance forms a high-Q notch filter and is presented at the input of the FTNF. The FTNF can be fully integrated in CMOS IC technology (or others, e.g., Bipolar, BiCMOS, and SiGe) and applied in wireless receiver systems including EDGE/GSM, Wideband Code Division Multiple Access (WCDMA), Bluetooth, and wireless LANs (e.g., IEEE 802.11). In addition, embodiments of a multi-band SAW-less RF receiver front-end and techniques to share components of FTNFs included within the multi-band SAW-less RF receiver front-end are presented.

Abstract: A programmable hybrid transmitter includes a baseband processing module, an up-conversion module, and a power amplifier circuit. The baseband processing module is coupled to convert outbound data into a complex signal when the programmable hybrid transmitter is in a first mode and to convert the outbound data into a normalized complex signal, offset information, and/or transmit property information when the programmable hybrid transmitter is in a second mode. The up-conversion module is coupled to mix the complex signal with a local oscillation to produce an up-converted signal when the programmable hybrid transmitter is in the first mode and to mix the normalized complex signal with the local oscillation based on the offset information to produce a normalized up-converted signal when the programmable hybrid transmitter is in the second mode.

Abstract: A supervisory communications device, such as a base station within a wireless network, monitors and controls communications with a plurality of remote communications devices, such as mobile nodes, throughout a widely distributed network, including the Internet. The supervisory device establishes the upstream slot structure and allocates upstream bandwidth by sending messages over its downstream channel. The supervisory device also uses the messages and minislot counts to anticipate bursts from the remote devices. Dual registers are provided within the supervisory device to generate minislot counts. A primary register generates minislot counts for a current slot structure, and a secondary register generates minislot counts for a revised slot structure. Software executed on the supervisory device determines a switchover time for changing to the revised slot structure and revised minislot count.

Abstract: One or more circuits in a mobile phone may be utilized for up sampling two or more audio signals to a same data sampling rate. Each audio signal, such as digital audio, voice, and polyringer, for example, may be received at one of a plurality of data sampling rates and one or more of the following wireless standards: WCDMA, HSDPA, GSM, GPRS, EDGE, and/or Bluetooth. Audio signals may be equalized and/or compensated with an FIR filter before up sampling or with an IIR filter to reduce overall processing latency. Multiple half-band interpolation operations may perform the up sampling. The first half-band filter may be replaced by an IIR filter to reduce overall processing latency. A gain of the up-sampled data may be adjusted to reduce noise effects. The channels of the up-sampled audio signals may be mixed and later further up sampled for subsequent communication to an output device.

Abstract: A control device that interacts with an entertainment system. The entertainment system drives a speaker device. The control device has a user interface that receives a user input identifying an audio selection and a language. At least one module of the control device transmits a control signal adapted to cause playing of audio information corresponding to the audio selection in the language identified by the user input on the entertainment system. The entertainment system may in addition drive a plurality of speaker devices. The control device may receive an additional language selection and cause playing of the audio information in a plurality of languages corresponding to the additional language selection on the plurality of speaker devices. Also for example, the control device may drive a second plurality of speaker devices. The control device may be adapted to receive media guide information and/or language guide information and present such information to a user.

Abstract: A system and method for convolutionally encoding a stream of bits are disclosed. An embodiment of the present invention provides improved communication system performance in comparison to existing convolutional coding, such as that proposed for use in systems employing multi-band, orthogonal frequency division multiplexed signaling. A generator polynomial having a native code rate R=1/3 may be used in combination with puncturing patterns supporting multiple codes rates. The resulting convolutional encoder exhibits improved performance at all code rates, and has no known disadvantages.

Abstract: A method and apparatus for communicating information between networked devices. Various aspects of the present invention may comprise, for example, a first networked device communicating information over a wireless communication network to a second networked device having power-save mode capability. The first networked device receives an incoming message from the second networked device. A first outgoing message is transmitted to the second networked device prior to transmitting a previously queued outgoing message. A second outgoing message is transmitted to the second networked device prior to the previously queued outgoing message being transmitted. Information may be communicated to the second networked device in a particular manner that depends on whether the second networked device has power-save capability. Communication medium access may be performed in a particular manner, depending on whether the second networked device has power-save capability.

Abstract: A system and method for preferred service flow of high priority messages between electronic devices is provided. The preferred service flow system includes preferred service flow queues, standard service flow queues, request/grant state machines and a controller. The method includes determining whether the standard processing rate of messages is acceptable, creating a preferred service flow queue and processing a high priority message through the preferred service flow queue. A preferred service flow queue will be created and the message processed using that queue when the standard processing rate is unacceptable and resources are available for the preferred service flow queue. If the standard processing rate is acceptable or resources are unavailable, a preferred service flow queue will not be created and the high priority message will be processed using the standard procedure for processing a message.

Abstract: A supervisory communications device, such as a base station within a wireless network, monitors and controls communications with a plurality of remote communications devices, such as mobile nodes, throughout a widely distributed network, including the Internet. The supervisory device establishes the upstream slot structure and allocates upstream bandwidth by sending messages over its downstream channel. The supervisory device also uses the messages and minislot counts to anticipate bursts from the remote devices. Dual registers are provided within the supervisory device to generate minislot counts. A primary register generates minislot counts for a current slot structure, and a secondary register generates minislot counts for a revised slot structure. Software executed on the supervisory device determines a switchover time for changing to the revised slot structure and revised minislot count.

Abstract: Aspects of a method and system for securing a network utilizing IPsec and MACsec protocols are provided. In one or more network nodes, aspects of the invention may enable conversion between Ethernet packets comprising payloads secured utilizing IPsec protocols and Ethernet packets secured utilizing MACsec protocols. For example, IPsec connections may be terminated at an ingress network node and IPsec connections may be regenerated at an egress network node. Packets secured utilizing MACsec protocols may be detected based on an Ethertype. Packets comprising payloads secured utilizing IPsec protocols may be detected based on a protocol field or a next header field. The conversion may be based on a data structure stored by and/or accessible to the network nodes. Aspects of the invention may enable securing data utilizing MACsec protocols when tunneling IPsec secured data through non-IPsec enabled nodes.

Abstract: Methods and systems for a multiple output capacitive buck/boost converter are disclosed and may include charging one or more input capacitors via an input voltage. One or more output voltages may be generated on a chip by switching the charged input capacitors to output capacitors via a switch array on the chip. The switch array may be controlled via a state machine. A constant current and/or voltage may be generated for the one or more output voltages via one or more current and/or voltage comparators. A variable resistance may be coupled in series with one or more switches in the switch array. The one or more input capacitors may be discrete capacitors external to the chip and/or integrated within the chip. One or more of the output voltages may be greater than the input voltage, or may be less than the input voltage.

Abstract: Video data is processed. A first high definition program stream is received that includes a first high definition video stream component. A first standard definition program stream is derived from the high definition program stream. A second standard definition is received having been derived from the first standard definition program stream. A second high definition program stream is derived from the second standard definition program stream and the first high definition video stream component.

Abstract: An integrated circuit includes a signal-path filter, a high-pass filter, and a control circuit. The signal-path filter is configured to receive an input signal and provide an output signal. The high-pass filter is coupled to the signal-path filter and is configured to reduce a direct-current (DC) component of the input signal. The high-pass filter includes a metal-oxide-semiconductor (MOS) switch, wherein a corner frequency of the high-pass filter is based on a resistance of the MOS switch. The control circuit is configured to provide a control voltage to the MOS switch. The control circuit includes a reference resistor, wherein the resistance of the MOS switch substantially tracks the resistance of the reference resistor. The integrated circuit may be embodied in software and/or included in a device (e.g., a mobile telephone) that receives and filters a signal.