Abstract: The present invention relates to a system and method for increasing the manufacturing yield of a plurality of memory cells used in cell arrays. A programmable fuse, having both hardware and software elements, is used with the plurality of memory cells to indicate that at least one memory cell is unusable and should be shifted out of operation. The software programmable element includes a programmable register adapted to shift in an appropriate value indicating that at least one of the memory cells is flawed. The hardware element includes a fuse gated with the programmable register. Shifting is indicated either by software programmable fuse or hard fuse. Soft fuse registers may be chained together forming a shift register.

Abstract: One or more methods and/or systems of utilizing a memory external to an integrated circuit chip are presented. In one embodiment, the system comprises an Integrated circuit containing a logic circuitry, a one time programmable memory, a control processor, and a data interface. In one embodiment, a method of storing data into a memory comprises programming one or more bits of a one time programmable memory, generating an Identifier from the integrated circuit chip, and using the identifier to store data within the memory.

Abstract: Modular, portable data collection terminals are disclosed for use in mixed wireless and hard-wired RF communication networks, wherein various radio transmitter modules and associated antennas may be selectively added to a base terminal unit to solve networking problems associated with specific types of business environments. Modularity exists in both the hardware (splitting data collection and processing control circuitry from radio transceiver control circuitry) and software (splitting transceiver specific, lower level communication protocol from generic, higher level communication protocol). The control circuitry, including associated microprocessors devices, interact to selectively activate communication circuits to perform necessary communication or data processing functions and enter and remain in a power-saving dormant state during other times. To support such dormant or “sleeping” states, a series of communication protocols provide for channel access to the communication network.

Abstract: A method and system for pipelined processing in an integrated embedded image and video accelerator is described. Aspects of a system for pipelined processing in an integrated embedded image and video accelerator may include circuitry that enables pipeline processing of video data within a single chip, wherein the pipeline processing may further include decoding of a block of video data while simultaneously inverse transforming a previously decoded block of video data. Aspects of the system may also include circuitry that enables transformation, within the single chip, of a block of said video data while simultaneously encoding, within said single chip, a previously transformed block of video data.

Abstract: An antenna structure includes first and second antennas. The first antenna has a first geometry corresponding to a first frequency. The second antenna has a second geometry corresponding to a second frequency. The second antenna is proximal to the first antenna and utilizes electrical-magnetic properties of the first antenna to transceive signals at the second frequency.

Abstract: The present invention provides a method for controlling transmission latency in a communications system, wherein the communications system is subject to a noise signal having at least a first noise phase and a second noise phase. The method includes determining a first bit rate for symbols transmitted during the first noise phase, and a second bit rate for symbols transmitted during the second noise phase, the first bit rate and the second bit rate being constrained such that a transmission latency does not exceed a pre-determined maximum allowed transmission latency; and transmitting symbols at the first bit rate during the first noise phase and at the second bit rate during the second noise phase. In other variants, the invention provides an apparatus, a constrained rate reciever, a transmitter and a signal.

Abstract: According to one exemplary embodiment, a memory sensing and latching circuit includes a sensing circuit for evaluating bit lines in a memory array and providing a sensed output. The memory sensing and latching circuit further includes a latching circuit including a dynamic one-shot circuit driven by the sensed output, a sense amplifier enable signal, and a precharge clock. The latching circuit further includes a storage circuit for storing a one-shot output of the dynamic one-shot circuit, where the one-shot output corresponds to the sensed output. The one-shot output of the dynamic one-shot circuit is stored in the storage circuit during an evaluation of the sensed output. The evaluation of the sensed output is responsive to the sense amplifier enable signal.

Abstract: A radio frequency identification (RFID) interface includes first coil, a plurality of coils, and a control module. The first coil is associated with an RFID tag and the plurality of coils is associated with an RFID reader. Each of the plurality of coils has a different orientation with respect to at least one axis of a multi-dimensional axis system. The control module is coupled to enable at least one of the plurality of coils based on electro-magnetic coupling between the first coil and the least one of the plurality of coils.

Abstract: A packet voice transceiver adapted to reside at a first end of a communication network and to send an ingress communication signal comprising voice packets to, and receive an egress communication signal comprising voice packets from, a second packet voice transceiver residing at a second end of the communication network. The packet voice transceiver includes a far-end echo canceller that reduces echo that is present in the egress communication signal. The far-end communicates with other functional components of the transceiver system and cancels echo or refrains from canceling echo based on the activity of the other functional components.

Abstract: In a wireless communication system, a method and system for implementing an FI function in a KASUMI algorithm for accelerating cryptography in GSM/GPRS/EDGE compliant handsets are provided. An efficient implementation of the FI function may comprise a first substitution stage and a second substitution stage, where a 9-bit substitution circuit and a 7-bit substitution circuit may be used in each of the stages. A pipe register may be used to transfer and zero-extend an input to the 7-bit substitution circuit for processing with an output of the 9-bit substitution circuit. A first multiplexer and a second multiplexer may be used to select the inputs for the substitution circuits at each one of the substitution stages. A third multiplexer and a fourth multiplexer may be used to select subkeys for encryption during the first substitution stage and zero value signals during the second substitution stage.

Abstract: A programmable antenna assembly includes a configurable antenna structure, a configurable antenna interface, and a control module. The configurable antenna structure includes a plurality of antenna elements that, in response to an antenna configuration signal, are configured elements into at least one antenna. The configurable antenna interface module is coupled to the at least one antenna and, based on an antenna interface control signal, provides at least one of an impedance matching circuit and a bandpass filter. The control module is coupled to generate the antenna configuration signal and the antenna interface control signal in accordance with a first frequency band and a second frequency band such that the at least one antenna facilitates at least one of transmitting and receiving a first RF signal within the first frequency band and facilitates at least one of transmitting and receiving a second RF signal within the second frequency band.

Abstract: A baseband processing module of a wireless terminal includes a Turbo decoding module. The Turbo decoding module decodes a Turbo code word to produce one or more Media Access Control (MAC) packet(s) carried by the turbo decode word. Each MAC packet includes a MAC packet header and the MAC packet payload, which carries one or more Radio Link Control (RLC) Packet Data Units (PDUs). The Turbo decoding module decodes the MAC packet header to determine boundaries of the PDUs carried in the MAC packet payload. The Turbo decoding module decodes RLC PDU headers and RLC PDU payloads of the RLC PDUs. The Turbo decoding module writes the decoded MAC packet header, the decoded RLC PDU headers, and the decoded RLC PDU payloads to memory in a word-aligned format. The Turbo decoding module may also operate in various other Turbo decoding modes.

Abstract: A system and method are used to provide uncorrelated code hopping in a communications system. A shift register receives data. The shift register is clocked to shift the data. A scaler performs a scaling operation on the data with a numerical value of active codes. A truncator truncates the scaled data to its seven most significant bits to produce a pseudo random hop number. A code matrix shifter circularly shifts the active codes in a code matrix based on the pseudo random hop number to produce a circularly shifted code. A transmitter transmits the circularly shifted code.

Abstract: Minimal hardware implementation of non-parity and parity trellis. More than one type of trellis can be represented using a minimal amount of hardware. In magnetic recording systems and other communication systems types, there is oftentimes a need to switch between trellises which support parity and ones which do not. Rules are presented herein which will ensure joint representation of more than one trellis while requiring minimal additional hardware when compared to representing only one trellis. To represent the non-parity trellis, emanating states, resultant states, and one or more expansion states (if needed) are all that is required. Any expansion states may also need to have its path metric and path memory corresponded to one of the resultant states to ensure proper detection according to the non-parity trellis.

Abstract: A sensor is implemented in an integrated circuit. The sensor includes one or more sensor pads that are provided at or near a surface of the integrated circuit. One or more integrated circuit components such as a sense amplifier are provided in the integrated circuit die adjacent the sensor pads. One or more other components are provided in the integrated circuit die adjacent the sensor pads.

Abstract: A differential amplifier with surge protection is described. The differential amplifier includes a first output driver device, a second output driver device, a first replica device, a second replica device, a current comparator, and a clamp circuit. The first replica device is configured to be a replica of the first output driver device. The second replica device is configured to be a replica of the second output driver device. The current comparator is configured to generate a threshold current, and to compare the threshold current to a first current through the first replica device and a second current through the second replica device. The clamp circuit is configured to limit a third current through the first output driver device and a fourth current through the second output driver device if the current comparator determines that the threshold current is greater than the first current or the second current.

Abstract: The present invention relates generally to analog-to-digital converters (ADCs). Embodiments of the present invention provide novel ADC architectures directed at reducing the overall ADC area and power consumption. Embodiments of the present invention may be used in pipelined ADCs, cyclic ADCs, and successive approximation (SAR) ADCs, for example. Further, embodiments of the present invention may be implemented using both single-ended and differential configurations.

Abstract: A method and apparatus for communicating between devices is described. In one embodiment, the method comprises running two or more instances of a switch MAC sublayer on a switch and managing the two or more instances of the switch MAC sublayer as multiple logical access points inside the switch.

Abstract: A physical layer device (PLD) includes a first serializer-deserializer (SERDES) device and a second SERDES device. Each SERDES device includes an analog portion with a serial port that is configured to communicate serial data with various network devices, and a digital portion that is configured to communicate parallel data with other various network devices. The PLD includes a first signal path that is configured to route serial data signals between the analog portions of the SERDES devices, bypassing the digital portions of the SERDES devices. Therefore, the SERDES devices can directly communicate serial data without performing parallel data conversion. A second signal path is configured to route recovered clock and data signals between the analog portions of the SERDES devices, but still bypassing the digital portions of the SERDES devices. The recovered clock and data signals are then regenerated before being transmitted over a network device.

Abstract: A method, system and computer program product for operation of a cable modem in response to Alternating Current (AC) power outage is described herein. When a loss of AC power is detected, the cable modem is switched to battery backup mode of operation using a single upstream and a single downstream channel. This switch occurs prior to receiving instructions from a cable modem termination system to use a single upstream and a single downstream channel. The cable modem notifies the cable modem termination system of the switch to battery backup mode of operation.