Abstract: A baseband controller system creates and maintains a schedule of synchronized events and reviews the schedule as a part of determining whether to initiate a transmission of a non-synchronous event (one that is not time sensitive, for example, e-mail). One aspect of the present invention is to create a system and method that avoids a possibility of collision between synchronized and non-synchronized communication events. A synchronized event is a scheduled transmission of time sensitive data such as what is often known as continuous bit rate data. Examples include video and voice wherein a collision (inability to transmit the continuous bit rate data) may result in degradation of signal quality at the receiving end. The inventive system and method evaluate the schedule of synchronized events in relation to the present time and determine whether a non-synchronized event may be transmitted without the likelihood of a collision.

Abstract: A system and method for mirroring power over Ethernet (PoE) registers in physical layer devices (PHYs) over a single isolation boundary. PHYs in a PoE system can be arranged in a master/slave configuration. In this configuration, a master PHY can be designed to communicate with the power source equipment controllers via a single isolation device.

Abstract: A network component for processing a packet includes at least one first storage unit, at least one second storage unit, at least one third storage unit, and an action implementation unit. The at least one first storage unit is configured to store an initial bit value selected from within the packet. The at least one second storage unit is configured to store a bit action length value. The at least one third storage unit is configured to store an extracted bit value based upon the initial bit value and the bit action length value. The action implementation unit is configured to implement at least one action on a packet by using an action bit value to modify the extracted bit value.

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.

Abstract: A beamforming radio frequency (RF) circuit includes a plurality of antennas, a plurality of amplifiers and an adjust module. The plurality of antennas is operably coupled to interrelate a plurality of beamformed signal components with a beamformed signal. The plurality of amplifiers is operably coupled to interrelate the plurality of beamformed signal components with a plurality of adjusted signal components. The adjust module is operably coupled to interrelate coordinates of a signal with the plurality of adjusted signal components.

Abstract: A method and system for automatically trunking ports connecting network devices arranged in a stacked configuration is provided. The method includes sending a packet, from a sending network device to at least one other receiving network device, through each of a plurality of ports of the network device. The packet includes at least an identifier for identifying the sending network device. The receiving network device maintains a table identifying which ports are connected to a neighboring network device.

Abstract: Methods and systems for diversity processing including using dedicated pilot method for open loop may include combining a plurality of received WCDMA/HSDPA multipath signals for each diversity transmit antenna to at least one processed diversity signal. The received WCDMA/HSDPA multipath signals may originate from diversity transmit antennas at a base station that may be transmitting information via a closed loop or open loop diversity transmission mode. Open loop symbols may be estimated using information from at least one common pilot channel. At least a portion of the at least one processed diversity signal may be despread from the at least one common pilot channel.

Abstract: A circuit and method utilizing a power control data bus for implementing power control. Various aspects of the present invention provide an electrical circuit that comprises a power supply circuit that outputs electrical power. The electrical circuit may also comprise an integrated circuit that receives electrical power from the power supply circuit. The electrical circuit may also comprise a power control data bus, which communicatively couples a power control data bus interface of the power supply circuit and a power control data bus interface of the integrated circuit. The power control data bus may, for example, carry power control data between the integrated circuit and the power supply circuit. Various aspects of the present invention also provide a method that comprises communicating power control data over a power control data bus and utilizing the power control data to control characteristics of electrical power provided to an integrated circuit or module.

Abstract: A system and method for providing a secure user interface in a shared resource environment. Various aspects of the present invention may comprise establishing a first wireless communication link between a first system and a user interface system. A first wireless communication port may, for example, establish such a wireless communication link. A first secure communication pathway may be established between the first system and the user interface system. A first secure communication module may, for example, establish such a secure communication pathway. A second wireless communication link may be established between a second system and the user interface system. A second wireless communication port may, for example, establish such a wireless communication link. A second communication pathway between the second system and the user interface system may be established. A second communication module may, for example, establish such a communication pathway.

Abstract: An integrated circuit comprising multiple independent power supply zones at substantially the same voltage level and a method for utilizing such power supply zones. An integrated circuit may comprise a first module and may, for example, comprise a second module. A first power supply bus may communicate first electrical power to the first module, where the first electrical power is characterized by a first set of power characteristics comprising a first voltage level. A second power supply bus may communicate second power to the second module, where the second power is characterized by a second set of power characteristics comprising a second voltage level that is substantially similar to the first voltage level. The second set of power characteristics may, for example, be substantially different than the first set of power characteristics. The second power supply bus may also, for example, communicate the second electrical power to the first module.

Abstract: A voltage supply interface provides both coarse and fine current control with reduced series resistance. The voltage supply interface has a segmented switch having N component switches that are digitally controlled. The voltage supply interface replaces a conventional sense resistor with a calibration circuit that has a replica switch that is a replica of the N component switches. The calibration circuit includes a reference current IREF that is sourced through the replica switch. A feedback amplifier forces a common voltage drop across the replica switch and the n-of-N activated component switches so that the cumulative current draw through the segmented switch is n·IREF. The current control of the voltage interface can be coarsely tuned by activating or deactivating component switches, and can be finely tuned by adjusting the reference current. The current sense resistor is eliminated so that the overall series resistance is lower.

Abstract: A circuit includes a first integrated circuit or die having a first circuit and a first inductive interface. A second integrated circuit or die has a second circuit and a second inductive interface. The first inductive interface and the second inductive interface are aligned to magnetically communicate signals between the first circuit and the second circuit.

Abstract: Synchronized UWB piconets for SOP (Simultaneously Operating Piconet) performance. A common backbone (either wired or wireless) is employed that provides a common CLK (clock signal) to all of the various PNCs (piconet coordinators) of various piconets that may operate within a sufficiently close region such that interference could undesirably occur. By providing a very reliable CLK signal from a common backbone to all of the PNCs of the various piconets operating within a substantially close proximity to one another, very precise synchronization may be ensured for all of the communications performed therein. The various piconets may then even operate using TDMA (Time Division Multiple Access)—whose performance would be substantially compromised without effective synchronization. In addition, combined TFC (time frequency code) and TDMA may also be employed to support the communications therein thereby providing even another degree of orthogonality that provided by TDMA alone.

Abstract: A method of determining a pitch period of an audio signal using a correlation-based signal derived from the audio signal. The correlation-based signal includes known peaks each corresponding to a respective one of known time lags. The known peaks includes a global maximum peak. The method comprises: (a) determining if a candidate peak among the local peaks exceeds a peak threshold; (b) determining if a candidate time lag corresponding to the candidate peak is within a predetermined range of at least one integer sub-multiple of the time lag corresponding to the global maximum peak; and (c) setting the pitch period equal to the candidate time lag when the determinations of both steps (a) and (b) are true.

Abstract: An HSDPA rake receiver has a plurality of rake fingers. Different channels may experience different spreading factors. The channel estimate (CE) and the CE delay may be affected and depend on the spreading factor. The CE delay is related to the individual rake finger output buffer size. According to the structure of the present invention, an adaptive channel estimate delay that depends on the spreading factor may result in improved performance.

Abstract: A method for wireless communication begins by determining whether legacy devices are within a proximal region of the wireless communication. The method continues, when at least one legacy device is within the proximal region, formatting a frame to include: a legacy preamble; a signal field; an extended preamble; at least one additional signal field; at least one service field; an inter frame gap; and a data field.

Abstract: An audio/video separator provides a high-performance and cost-effective solution to analog TV reception with only one A/D converter and a minimum of analog IF components. The apparatus may operate on a digitized TV signal and, when integrated with a digital video processor, process video signals while separating audio signals. The resultant audio and video signals may be considered to have excellent signal quality due to highly optimized demodulation architecture and digital signal processing techniques on both audio and video data paths.

Abstract: Inter-device adaptable interfacing clock skewing. The invention is operable in either one of both of a transmit mode and a receive mode to perform skewing of a transmitted and/or a received signal. The operational parameters including frequency and phase may be determined during auto detect/auto negotiation, they may be programmed externally, or they may be user selected in various embodiments. A device may include a clock generator, one or more divider, and one or more delay cells internally to the device. If desired, a high frequency clock is generated within the device and then divided down to generate the appropriate clock signal that supports the communication and interaction between multiple devices. Registers and/or pins may be used to select the clock frequency and phase of output clock signals. The present invention supports multiple Ethernet protocols between multiple devices including 10BaseT, 100BaseT, and 1000BaseT.

Abstract: A communication infrastructure includes an intermediate routing node that routes a plurality of packets between a source device and a plurality of destination devices, a plurality of templates stored on the intermediate routing node and a service function. The intermediate routing node, e.g., a switch, router, access point, bridge, or gateway, identifies packets containing requests for a webpage, the requests being a service attack attempt by comparing the packet with the plurality of templates. Then, the intermediate routing node denies service attack by interacting with the server and client devices. That is, the intermediate routing node sends messages with challenge mechanism to the server, based on the response or otherwise, sends messages and anti-service attack downloads to the client devices and receives response.

Abstract: A method leverages knowledge of the actual or ideal bit sequence to improve the performance of any sequence detector. This improved performance results by constraining the sequence detector when the sequence detector has knowledge of known patterns within the sample sequence. Embodiments may control or limit the effects of ISI on a readback signal in order to allow higher storage within physical media such as that of a HDD. This method involves reading an analog waveform from the physical media. The phase of this analog waveform is determined and it is sampled at regular intervals using a timing recovery scheme. This sample sequence is equalized (filtered) and sent to a sequence detector which will compare the received sequence to all possible transmitted sequences, generating a path through a trellis that represents the estimated sequence. That trellis path may pass through known states at certain times. This knowledge makes it possible to remove some of the paths under consideration.