Abstract: Digital divider for low voltage LOGEN. LOGEN is a local oscillator generator. One implementation presented herein provides for a pseudo-complementary metal-oxide-semiconductor (CMOS), in that, it is not a true CMOS type circuitry that has no DC current dissipation, but nevertheless does operate well at relatively high frequencies and relatively low power supply voltage levels. Appropriately placed p-channel metal oxide semiconductor field-effect transistors (P-MOSFETs) and n-channel MOSFETs (e.g., N-MOSFETs) are employed to provide for an all digital divider circuitry. In some embodiments, four active circuitry element levels are stacked between a power supply voltage and ground voltage level. In other embodiments, three active circuitry element levels are stacked between a power supply voltage and ground voltage level. The three active circuitry element levels embodiment provides for a greater area savings (e.g.

Abstract: Disclosed is a double data rate (DDR) input block comprising first and second input registers corresponding to a DDR input of the DDR input block. The first and second input registers are coupled to the DDR input. The DDR input block is configured to load a first data into the first input register and a second data into the second input register during a single clock cycle of a system clock, thereby operating at double data input during a single clock cycle. A single data rate/double data rate (SDR/DDR) input block may be operated in either SDR or DDR mode. The DDR input block may he used with a scannable output reduction block. The DDR input block may be used in systems utilizing a content addressable memory (CAM) or a random access memory (RAM), or other types of memory devices.

Abstract: An apparatus for tracking a real time clock comprising a delay element for receiving a first clock signal and providing a second delayed clock signal, a quadrature interface including a first input and a second input for respectively receiving the first and second clock signals, control logic adapted to provide a state machine including four states, the four states respectively corresponding to a 2-bit gray code such that a current state is selected by determining a correspondence of the first and second inputs to the 2-bit gray code and a counter is incremented upon a transition between a first state and a second state of the state machine.

Abstract: Communications signal transcoder. A solution is provided to transcode a signal from a first signal type to a second signal type to ensure proper interfacing between devices that may operate using different signal types. For example, within a communication system, a first signal type (having a first modulation type, e.g., 8 PSK) may be received. The transcoder then ensures that this signal, after it has undergone any initial processing (such as tuning, down-converting, decoding, and so on), is encoded into a second signal type (having a second modulation type, e.g., QPSK) such that it can interface properly with a device for which the received signal is intended. This transcoder functionality may be implemented within discrete components, or it may alternatively be integrated within a functional block of an integrated circuit. This functionality may be implemented in a variety of communication systems including satellite, cable television, Internet, and others.

Abstract: A hybrid on-chip-off-chip transformer includes an off-chip winding section and an on-chip winding section. The off-chip winding section is coupled to produce a first electromagnetic signal from a reference source. The on-chip winding section is coupled to derive a second electromagnetic signal from the first electromagnetic signal when the on-chip winding section is with in a proximal coupling distance of the off-chip winding section.

Abstract: A Power-over-Ethernet (PoE) communication system dynamically provides power and data communications over a communications link. In a computing environment made up of one or more personal computing devices (PCD) and/or one or more powered devices (PD), power source equipment (PSE) determines an allocated amount of power to be supplied to each device. The personal computing devices include a unified LAN-On-Motherboard (LOM) that combines the functionality of a powered device (PD) controller of a conventional PD and a LOM of a conventional personal computing device into a single unified subsystem. The unified LOM includes a standard or universal interface between the LOM and PD controller so that different types of PD devices with differing functionality can be easily married to the LOM, without requiring significant hardware or software redesign.

Abstract: A method, system, and computer program product for receiving and resequencing a plurality of data segments received on a plurality of channels of a bonding channel set, comprising determining if a sequence number of a received segment matches an expected sequence number. If so, the process includes forwarding the segment for further processing, incrementing the expected sequence number; and forwarding any queued packets corresponding to the expected sequence number and immediately succeeding sequence numbers less than a sequence number of annexed missing segment. If the sequence number of the received segment does not match the expected sequence number, the received segment is queued at a memory location. The address of this location is converted to a segment index. The segment index is stored in a sparse array.

Abstract: A multimode communication integrated circuit comprising baseband processing circuitry with a shared radio interface. Various aspects of the present invention may comprise a processor module adapted to perform various processing (e.g., baseband processing) in support of multimode communications. A first radio module may be communicatively coupled to the processor module through a common communication interface. A second radio module may also be communicatively coupled to the processor module through the common communication interface. The common communication interface may, for example, be adapted to communicate information over a communication bus that is shared between the processor module and a plurality of radio modules (e.g., the first and second radio modules).

Abstract: High-resolution low-interconnect phase rotator. A signal may be generated having any desired phase (as determined by the step size employed). First and second control signals select a sector (e.g., the range from 0° to 360° is divided into a number of sectors) and a particular phase within that sector. Generally, this range from 0° to 360° is uniformly divided so that each sector is the same. However, if desired, there can alternatively be differences in the sizes of each of the sectors. The use of these two sets of controls signals (one for selecting the sector and one for selecting the particular phase within the sector) allows for very few control signals. N-channel metal oxide semiconductor field-effect transistor (N-MOSFET) based switches and differential pairs of transistors or alternatively p-channel metal oxide semiconductor field-effect transistor (P-MOSFET) based switches and differential pairs of transistors can be employed.

Abstract: A system for managing data in multiple data processing devices using common data paths. Embodiments of the invention comprise a first data processing system comprising a cacheable coherent memory space; and a second data processing system communicatively coupled to the first data processing system with the second data processing system comprising at least one bridge, wherein the bridge is operable to perform an uncacheable remote access to the cacheable coherent memory space of the first data processing system. In some embodiments, the access performed by the bridge comprises a data write to the memory of the first data processing system for incorporation into the cacheable coherent memory space of the first data system. In other embodiments, the access performed by the bridge comprises a data read from the cacheable coherent memory space of the first data system.

Abstract: A system and method that abstracts an interrupt from a group of interrupts, which may occur in a module, to call another module. Abstracting one interrupt from a group of interrupts allows the called module to deal with only one interrupt. The choice of the interrupt may be based on the configuration of the module from which the interrupts are originated. In an embodiment of the present invention, the abstracted interrupt triggers an event. When the triggered event is completed, an interrupt may be fired off to the target module. An interrupt handler in the target module or an external interrupt handler may handle the interrupt that calls the target module.

Abstract: An impedance transformer includes a first winding and a second winding. The first winding includes a first plurality of winding components, wherein each of the first plurality of winding components is on a corresponding layer of a first set of layers of a supporting substrate. The second winding includes a second plurality of winding components, wherein each of the second plurality of winding components is on a corresponding layer of a second set of layers of the supporting substrate and the first and second sets of layers are interleaved. The first winding has a first impedance within a desired frequency range and the second winding has a second impedance within the desired frequency range, where the first and second impedances are based on at least one of spacing, trace width, and trace length of the first and second plurality of winding components.

Abstract: An integrated digital BTSC encoder with an improved pilot signal generator substantially implemented on a single CMOS integrated circuit. By digitally generating a sinusoid that is frequency locked to a two-state input reference signal using a high rate internal clock, a hardware-efficient BTSC pilot signal generator is provided with good acquisition and tracking performance. Implemented efficiently as a simple phase detector, a low-complexity loop filter, a pilot frequency offset adder, a phase accumulator and a sinusoidal generator, the invention enables lower-rate post-processing of the pilot tone without a costly variable interpolator decimator structures.

Abstract: Combined LDPC (Low Density Parity Check) encoder and syndrome checker. A novel approach is presented by which the encoding processing and at least a portion of the decoding processing of an LDPC coded signal can be performed using a shared circuitry. The LDPC encoding processing and syndrome calculation operations (in accordance with the LDPC decoding processing) can be performed using a common circuitry having a portion of which whose connectivity is only slightly modified depending on whether encoding or decoding is being performed. To effectuate this selection (between encoding and decoding), any of a variety of means can be employed including the use of multiplexers that are operable to select a first connectivity (for encoding) and a second connectivity (for decoding). This can result in a hardware savings of space, cost, and complexity since a shared circuitry can perform both encoding and at least part of the decoding processing.

Abstract: A method and apparatus are disclosed for efficiently de-scrambling one or more bytes of data according to DSL standards on a processor. This is achieved by providing an instruction for de-scrambling one or more bytes of data according to the DSL standards. Accordingly, the invention advantageously provides a processor with the ability to de-scramble data with a single instruction thus allowing for more efficient and faster de-scrambling operations for subsequent processing.

Abstract: Enhanced polar modulator for transmitter. Within a phase locked loop (PLL), a two point modulation topology is employed in which phase information passes through a limiter (e.g., a +90° or +re/2) in which the phase information dynamic range is divide by a factor (e.g., by 2) and a maximum frequency deviation is also divided by a factor (e.g., by 2). Then, a double balanced up-converter mixer/modulator is implemented to perform gain adjustment (e.g., magnitude and/or amplitude adjustment) and phase changes of 0° and +180° or 0 and +re (e.g., negative gains values may be employed). Phase adjustment in such an architecture is split and provided to both the PLL and to the mixer/modulator of such a polar modulator within a transmitter module such as may be implemented within a communication device (e.g., which may be a wireless communication device). This architecture that includes a PLL with a double balanced up-converter mixer/modulator suppresses even harmonics.

Abstract: A wireless terminal having processing resources, a user interface including a user input device and a display, and a wireless interface causes a file to be printed to a destination printer that is unsupported by the wireless terminal. The processing resources communicatively couple to the wireless interface and to the user interface and are operable to receive a file via a servicing wireless network and the wireless interface, receive a request via the user interface to print the file, identify a destination printer, determine that the wireless terminal does not support printing of the file at the destination printer, identify a servicing device for processing of the file for printing at the destination printer, and transmit the file to the servicing device via the wireless interface and the servicing wireless network.

Abstract: An apparatus and method for local oscillator calibration compensates for filter passband variation in a mixer circuit, such as a receiver circuit. The receiver includes at least a mixer circuit and a filter coupled to the output of the mixer. During operation, the mixer mixes an RF input signal with a first local oscillator (LO) signal to frequency translate a selected channel in the RF input signal into the passband of the filter. During a calibration mode, the RF input signal is disabled, and the first LO signal is injected into the filter input by leaking the first LO signal through the mixer circuit. The frequency of the LO signal is then swept over a frequency bandwidth that is sufficiently wide so that the actual passband is detected by measuring the signal amplitude at the output of the bandpass filter, thereby determining any variation in the passband of the filter from the expected passband.

Abstract: An IP network includes a central entity and at least one customer premises equipment (CPE) device. The central entity generates a program clock reference (PCR) clock and provides audio-visual packets to a CPE based on the PCR clock. The CPE sets a first clock based on the PCR clock for decoding operations. The CPE sets a second clock that is independent from the first clock for audio and video output operations. For example, the CPE can process the audio-visual packets using the second clock.

Abstract: A method of communicating data to a receiving antenna from N transmitting antennas, where N is an integer, includes the steps of determining whether a legacy transmission mode has been selected, producing N data streams from outbound data, and applying the N data streams to a space/time encoder to produce N encoded signals. When the legacy transmission mode has not been selected, the N encoded signals are transmitting from N transmitting antennas and when the legacy transmission mode has been selected, the one encoded signal is transmitted from one of the N transmitting antennas. The legacy transmission mode allows receivers to receive and process transmitted signals when the receivers are only configured to receive the transmitted signals from a single transmitting antenna.