Abstract: Aspects of a method and system for processing signals via an integrated low noise amplifier having a configurable input signaling mode are provided. For an unbalanced input signal, a first input terminal of the LNA may be communicatively coupled to ground via an inductance and a bias point of the LNA may be communicatively coupled to a first bias voltage. For a balanced input signal, the first input terminal of the LNA may be communicatively coupled to the balanced signal and the bias point may be communicatively coupled to a second bias voltage. The LNA may comprise a center-tapped differential inductor which may be coupled to an output terminal of the LNA and may enable the LNA to output differential signals regardless of the input signaling mode. In various embodiments of the invention, the LNA may be utilized to amplify GNSS signals such as GPS signals.

Abstract: A method for packaging an integrated circuit. A barrier metal pattern is disposed on a baseplate. A conductive layer is disposed on the barrier metal pattern. A photoresist having a pattern is applied to the conductive layer. A via is then disposed on the conductive layer. An integrated circuit is coupled to the via and encapsulated. Then, at least a part of the baseplate is removed. An integrated circuit package is produced by the method.

Abstract: Certain aspects of reducing power consumption in communication devices may comprise deasserting a signal indicating that an on-chip UART may be ready to receive data. The deasserted signal may be asserted when the on-chip UART is not ready to receive data. The deasserted signal and asserted signal may be a RTS signal or a CTS signal. The signal may be deasserted when an on-chip processor wakes up from a low power state. The deasserted signal may be asserted when an on-chip processor enters a low power state. The on-chip UART may be adapted to receive and process data from an off-chip processor when the signal is deasserted. The data may be queued externally to the on-chip UART by an off-chip processor when the deasserted signal is asserted. The on-chip UART may be adapted to receive an interrupt signal that causes it to wake up from a low power state.

Abstract: The present invention is directed to an apparatus and method for reducing a parasitic capacitance in an integrated circuit. The apparatus includes a substrate and a biasing device. The substrate has a circuit disposed thereon, wherein a first capacitance exists between the substrate and an element of the circuit. The biasing device DC biases a first portion of the substrate to a voltage different than a voltage of a second portion of the substrate, thereby inducing a second capacitance between the first portion of the substrate and the second portion of the substrate. The second capacitance is in series with the first capacitance.

Abstract: A physical layer device (PLD) includes a first serializer-deserializer (SERDES) device and a second SERDES device. Each SERDES device includes an analog portion with a serial port that is configured to communicate serial data with various network devices, and a digital portion that is configured to communicate parallel data with other various network devices. The PLD includes a first signal path that is configured to route serial data signals between the analog portions of the SERDES devices, bypassing the digital portions of the SERDES devices. Therefore, the SERDES devices can directly communicate serial data without performing parallel data conversion. A second signal path is configured to route recovered clock and data signals between the analog portions of the SERDES devices, but still bypassing the digital portions of the SERDES devices. The recovered clock and data signals are then regenerated before being transmitted over a network device.

Abstract: A method and system for a bandwidth efficient medium access control (MAC) protocol is provided, which may comprise communicating a request to transmit (RTS) signal to a receiving station to determine if a channel is available for transmission. A clear to send (CTS) acknowledgement signal may be received from the receiving station if the channel is available for transmission. A plurality of medium access control (MAC) protocol data unit (MPDU) fragments separated by a point coordination function (PCF) interframe space (PIFS) interval may be transmitted in response to the received CTS acknowledgement signal.

Abstract: A method and system for improving reception in wired and wireless systems through redundancy and iterative processing are provided. A multilayer decoding process may comprise a burst process and a frame process. Results from a first burst process may be utilized to generate a decoded bit sequence in the frame process. The frame process may utilize redundancy information and physical constraints to improve the performance of a decoding algorithm. Results from the frame process may be fed back for a second iteration of the burst process and of the frame process, to further improve the decoding operation. In some instances, the second iteration of the burst process may be based on a gradient search approach.

Abstract: Traditionally, system loads are placed in parallel with the battery. This simple topology wastes the available power if the USB power and/or wall adapter is present. Recent topologies have made some improvements by powering the load by the maximum available voltage. Thus, if a USB power source or wall adapter is present, the load is powered by them rather than the battery, thus improving the system efficiency. However, since the USB power and wall adapter power are current limited, if the load requires higher current than the current limited USB or adapter, then the entire system is powered at voltage of the battery. The present invention further improves the system efficiency by distinguishing the load and powering the constant power loads by the maximum voltage and placing the constant current loads in parallel with the battery.

Abstract: Certain aspects of a method and system for programmable biasing mechanism for a mobile digital television environment are disclosed. Aspects of one method may include controlling a bias of components within each of a plurality of radio frequency (RF) front-ends that comprise low noise amplifiers (LNAs) integrated within a single chip multi-band RF receiver, and of components within each of a plurality of baseband processors integrated within the single chip multi-band RF receiver. The controlling of the bias is based on signal power measurements within the integrated RF front-ends and within the baseband processors, and each of the plurality of RF front-ends handles processing of at least one of: a received UHF signal and a received L-band signal.

Abstract: An integrated circuit includes an on-chip antenna interface, coupled to an off-chip antenna interface having at least one off-chip filter component that forms a programmable filter with the at least one off-chip filter component. The programmable filter is programmable based on a control signal. An RF receiver generates inbound data in response to a received signal from the programmable filter.

Abstract: A voice data and RF integrated circuit (IC) receives at least one power status signal indicating an inductive power status of an off-chip inductive power module, the inductive power status including an inductive power ready state, and the at least one power status signal further indicating a battery power status of a battery. A selected one of a plurality of power modes is determined based on the at least one power status signal. A power mode signal is generated based on the selected one of the plurality of power modes. A plurality of power supply signals are generated based on the power mode signal.

Abstract: A circuit and method utilizing a power control data bus for implementing power control. Various aspects of the present invention provide an electrical circuit that comprises a power supply circuit that outputs electrical power. The electrical circuit may also comprise an integrated circuit that receives electrical power from the power supply circuit. The electrical circuit may also comprise a power control data bus, which communicatively couples a power control data bus interface of the power supply circuit and a power control data bus interface of the integrated circuit. The power control data bus may, for example, carry power control data between the integrated circuit and the power supply circuit. Various aspects of the present invention also provide a method that comprises communicating power control data over a power control data bus and utilizing the power control data to control characteristics of electrical power provided to an integrated circuit or module.

Abstract: Aspects of a method and system for a radio data service (RDS) demodulator for a single chip integrated Bluetooth and frequency modulation (FM) transceiver and baseband processor are presented. Aspects of the system may include circuitry on a single chip that enables demodulation of an RDS signal, filtering of the RDS signal, and detection of binary bits in the filtered RDS signal. The filtered RDS signal may be generated by filtering the RDS signal based on a raised cosine filter, or a doublet filter. In general, the RDS signal may also be filtered by a filter that is a first, or greater derivative of a Gaussian filter in either the time or frequency domain. Aspects of the method may include demodulating the RDS signal, filtering the RDS signal, and detecting binary bits in the filtered RDS signal.

Abstract: A system and method for providing a secure user interface in a shared resource environment. Various aspects of the present invention may comprise establishing a first wireless communication link between a first system and a user interface system. A first wireless communication port may, for example, establish such a wireless communication link. A first secure communication pathway may be established between the first system and the user interface system. A first secure communication module may, for example, establish such a secure communication pathway. A second wireless communication link may be established between a second system and the user interface system. A second wireless communication port may, for example, establish such a wireless communication link. A second communication pathway between the second system and the user interface system may be established. A second communication module may, for example, establish such a communication pathway.

Abstract: Methods and systems for detecting defects in serial link transceivers. Defect detection includes detecting open circuits in one or more of the transmission lines, detecting short circuits between one or more of the transmission lines and a power supply, detecting short circuits between the transmission lines, or detecting short circuits across optional AC-couplings in the transmission lines. The detection can include direct or indirect detection of voltage or current.

Abstract: A (radio frequency) RF reception system includes an off-chip antenna interface and an integrated circuit. The an off-chip antenna interface includes at least one first off-chip impedance matching component, a filter, and at least one second off-chip impedance matching component. The integrated circuit includes an on-chip antenna interface that forms a first programmable impedance matching network with the at least one first off-chip impedance matching component, and forms a second programmable impedance matching network with the at least one second off-chip impedance matching component. The first programmable impedance matching network and the second programmable impedance matching network are programmable based on a frequency selection signal.

Abstract: Certain embodiments of a method and system for safe and efficient power down and drawing minimal current when a device is not enabled may comprise receiving within a network adapter chip (NAC) a signal that indicates a reduced power mode. Based on this signal, the NAC may control an off-chip voltage source that provides reduced voltage to circuitry within the NAC. The off-chip voltage source, which may comprise a first PNP transistor and a second PNP transistor, may reduce a voltage to a first voltage and a second voltage. The NAC may also reduce current through the off-chip voltage source to approximately zero amperes and an output voltage of the off-chip voltage source to approximately zero volts. The first voltage and/or the second voltage may be fed back to control the output voltage and current of the off-chip voltage source.

Abstract: In one embodiment of the communications network, the predetermined encoding scheme and symbol constellation configurations are chosen so that the range in channel qualities that the encoding scheme and symbol constellation configurations are designed to be utilized within overlap with each other. This overlapping provides hysteresis, which reduces the frequency with which a subscriber must alter encoding scheme and symbol constellations. Reducing the frequency of changing encoding scheme and/or symbol constellation eliminates the communication overhead associated with these changes and increases throughput by enabling the subscriber to spend more time transmitting data.

Abstract: The present invention relates to the field of (micro)computer design and architecture, and in particular to microarchitecture associated with moving data values between a (micro)processor and memory components. Particularly, the present invention relates to a computer system with an processor architecture in which register addresses are generated with more than one execution channel controlled by one central processing unit with at least one load/store unit for loading and storing data objects, and at least one cache memory associated to the processor holding data objects accessed by the processor, wherein said processor's load/store unit contains a high speed memory directly interfacing said load/store unit to the cache and directly accessible by the cache memory for implementing scatter and gather operations. The present invention improves the performance of architectures with dual ported microprocessor implementations comprising two execution pipelines capable of two load/store data transactions per cycle.

Abstract: A system on a chip for network devices. In one implementation, the system on a chip may include (integrated onto a single integrated circuit), a processor and one or more I/O devices for networking applications. For example, the I/O devices may include one or more network interface circuits for coupling to a network interface. In one embodiment, coherency may be enforced within the boundaries of the system on a chip but not enforced outside of the boundaries.